494 lines
25 KiB
C
494 lines
25 KiB
C
/****************************************************************************
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* arch/z80/src/ez80/ez80f91.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_Z80_SRC_EZ80_EZ80F91_H
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#define __ARCH_Z80_SRC_EZ80_EZ80F91_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "ez80f91_emac.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Memory map ***************************************************************/
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#define EZ80_ONCHIPFLASH 0x000000 /* CS0: 256Kb of on-chip flash */
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#define EZ80_OFFCHIPCS0 0x400000 /* CS0: Off chip use (usually flash) */
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#define EZ80_OFFCHIPCS2 0x800000 /* CS2: Off chip use (e.g. memory mapped I/O) */
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#define EZ80_OFFCHIPCS1 0xc00000 /* CS1: Off chip use (usually SRAM) */
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#define EZ80_EMACSRAM 0xffc000 /* On-chip EMAC SRAM (8Kb) on reset*/
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#define EZ80_ONCHIPSRAM 0xffe000 /* On-chip SRAM (8Kb) on reset */
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#define EZ80_FLASH_SIZE 0x040000 /* 256Kb on-chip flash */
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#define EZ80_SRAM_SIZE 0x002000 /* 8Kb on-chip sram */
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/* Product ID Registers ****************************************************/
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#define EZ80_ZDI_ID_L 0x00
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#define EZ80_ZDI_ID_H 0x01
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#define EZ80_ZDI_ID_REV 0x02
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/* Interrupt Registers *****************************************************/
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#define EZ80_INT_P0 0x10
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#define EZ80_INT_P1 0x11
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#define EZ80_INT_P2 0x12
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#define EZ80_INT_P3 0x13
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#define EZ80_INT_P4 0x14
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#define EZ80_INT_P5 0x15
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/* EMACC Registers *********************************************************/
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#define EZ80_EMAC_TEST 0x20 /* EMAC test register */
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#define EZ80_EMAC_CFG1 0x21 /* EMAC configuration 1 register */
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#define EZ80_EMAC_CFG2 0x22 /* EMAC configuration 2 register */
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#define EZ80_EMAC_CFG3 0x23 /* EMAC configuration 3 register */
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#define EZ80_EMAC_CFG4 0x24 /* EMAC configuration 4 register */
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#define EZ80_EMAC_STAD_0 0x25 /* EMAC station address register 0 */
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#define EZ80_EMAC_STAD_1 0x26 /* EMAC station address register 1 */
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#define EZ80_EMAC_STAD_2 0x27 /* EMAC station address register 2 */
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#define EZ80_EMAC_STAD_3 0x28 /* EMAC station address register 3 */
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#define EZ80_EMAC_STAD_4 0x29 /* EMAC station address register 4 */
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#define EZ80_EMAC_STAD_5 0x2a /* EMAC station address register 5 */
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#define EZ80_EMAC_TPTV_L 0x2b /* Transit pause timer value (low) */
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#define EZ80_EMAC_TPTV_H 0x2c /* Transit pause timer value (high) */
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#define EZ80_EMAC_IPGT 0x2d /* EMAC Interpacket gap register */
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#define EZ80_EMAC_IPGR1 0x2e /* Non-back-to-back IPG register 1 */
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#define EZ80_EMAC_IPGR2 0x2f /* Non-back-to-back IPG register 2 */
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#define EZ80_EMAC_MAXF_L 0x30 /* EMAC maximum frame length register (low) */
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#define EZ80_EMAC_MAXF_H 0x31 /* EMAC maximum frame length register (high) */
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#define EZ80_EMAC_AFR 0x32 /* EMAC address filter register */
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#define EZ80_EMAC_HTBL_0 0x33 /* EMAC hash table register 0 */
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#define EZ80_EMAC_HTBL_1 0x34 /* EMAC hash table register 1 */
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#define EZ80_EMAC_HTBL_2 0x35 /* EMAC hash table register 2 */
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#define EZ80_EMAC_HTBL_3 0x36 /* EMAC hash table register 3 */
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#define EZ80_EMAC_HTBL_4 0x37 /* EMAC hash table register 4 */
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#define EZ80_EMAC_HTBL_5 0x38 /* EMAC hash table register 5 */
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#define EZ80_EMAC_HTBL_6 0x39 /* EMAC hash table register 6 */
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#define EZ80_EMAC_HTBL_7 0x3a /* EMAC hash table register 7 */
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#define EZ80_EMAC_MIIMGT 0x3b /* EMACS MII management register */
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#define EZ80_EMAC_CTLD_L 0x3c /* PHY configuration data register (low) */
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#define EZ80_EMAC_CTLD_H 0x3d /* PHY configuration data register (high) */
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#define EZ80_EMAC_RGAD 0x3e /* PHY address register */
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#define EZ80_EMAC_FIAD 0x3f /* PHY unit select register */
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#define EZ80_EMAC_PTMR 0x40 /* EMAC transmit polling timer register */
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#define EZ80_EMAC_RST 0x41 /* EMAC reset control register */
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#define EZ80_EMAC_TLBP_L 0x42 /* EMAC transmit lower boundary pointer (low) */
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#define EZ80_EMAC_TLBP_H 0x43 /* EMAC transmit lower boundary pointer (high) */
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#define EZ80_EMAC_BP_L 0x44 /* EMAC boundary pointer register (low) */
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#define EZ80_EMAC_BP_H 0x45 /* EMAC boundary pointer register (high) */
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#define EZ80_EMAC_BP_U 0x46 /* EMAC boundary pointer register (upper byte) */
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#define EZ80_EMAC_RHBP_L 0x47 /* EMAC receive high boundary pointer register (low) */
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#define EZ80_EMAC_RHBP_H 0x48 /* EMAC receive high boundary pointer register (high) */
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#define EZ80_EMAC_RRP_L 0x49 /* EMAC receive read pointer (low) */
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#define EZ80_EMAC_RRP_H 0x4a /* EMAC receive read pointer (high) */
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#define EZ80_EMAC_BUFSZ 0x4b /* EMAC buffer size register */
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#define EZ80_EMAC_IEN 0x4c /* EMAC interrupt enable register */
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#define EZ80_EMAC_ISTAT 0x4d /* EMAC interrupt status register */
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#define EZ80_EMAC_PRSD_L 0x4e /* PHY read status data register (low) */
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#define EZ80_EMAC_PRSD_H 0x4f /* PHY read status data register (high) */
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#define EZ80_EMAC_MIISTAT 0x50 /* EMAC MII status register */
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#define EZ80_EMAC_RWP_L 0x51 /* EMAC receive write pointer (low) */
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#define EZ80_EMAC_RWP_H 0x52 /* EMAC receive write pointer (high) */
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#define EZ80_EMAC_TRP_L 0x53 /* EMAC transmit read pointer (low) */
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#define EZ80_EMAC_TRP_H 0x54 /* EMAC transmit read pointer (high) */
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#define EZ80_EMAC_BLKSLFT_L 0x55 /* EMAC receive blocks left register (low) */
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#define EZ80_EMAC_BLKSLFT_H 0x56 /* EMAC receive blocks left register (high) */
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#define EZ80_EMAC_FDATA_L 0x57 /* EMAC FIFO data register (low) */
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#define EZ80_EMAC_FDATA_H 0x58 /* EMAC FIFO data register (high) */
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#define EZ80_EMAC_FFLAGS 0x59 /* EMAC FIFO flags register */
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/* PLL Registers ***********************************************************/
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#define EZ80_PLL_DIV_L 0x5c
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#define EZ80_PLL_DIV_H 0x5d
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#define EZ80_PLL_CTL0 0x5e
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#define EZ80_PLL_CTL1 0x5f
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/* Timer Registers *********************************************************/
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#define EZ80_TMR0_CTL 0x60 /* RW: Timer 0 control register */
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#define EZ80_TMR0_IER 0x61 /* RW: Timer 0 interrupt enable register */
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#define EZ80_TMR0_IIR 0x62 /* R : Timer 0 interrupt ID register */
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#define EZ80_TMR0_DRL 0x63 /* R : Timer 0 data register (low) */
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#define EZ80_TMR0_DRH 0x64 /* R : Timer 0 data register (high) */
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#define EZ80_TMR0_RRL 0x63 /* W: Timer 0 reload register (low) */
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#define EZ80_TMR0_RRH 0x64 /* W: Timer 0 reload register (high) */
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#define EZ80_TMR1_CTL 0x65 /* RW: Timer 1 control register */
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#define EZ80_TMR1_IER 0x66 /* RW: Timer 1 interrupt enable register */
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#define EZ80_TMR1_IIR 0x67 /* R : Timer 1 interrupt ID register */
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#define EZ80_TMR1_DRL 0x68 /* R : Timer 1 data register (low) */
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#define EZ80_TMR1_DRH 0x69 /* R : Timer 1 data register (high) */
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#define EZ80_TMR1_RRL 0x68 /* W: Timer 1 reload register (low) */
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#define EZ80_TMR1_RRH 0x69 /* W: Timer 1 reload register (high) */
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#define EZ80_TMR1_CAPCTL 0x6a /* RW: Timer 1 input capture control register */
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#define EZ80_TMR1_CAPAL 0x6b /* R : Timer 1 capture input value A (low) */
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#define EZ80_TMR1_CAPAH 0x6c /* R : Timer 1 capture input value A (high) */
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#define EZ80_TMR1_CAPBL 0x6d /* R : Timer 1 capture input value B (low) */
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#define EZ80_TMR1_CAPBH 0x6e
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#define EZ80_TMR2_CTL 0x6f /* RW: Timer 2 control register */
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#define EZ80_TMR2_IER 0x70 /* RW: Timer 2 interrupt enable register */
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#define EZ80_TMR2_IIR 0x71 /* R : Timer 2 interrupt ID register */
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#define EZ80_TMR2_DRL 0x72 /* R : Timer 2 data register (low) */
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#define EZ80_TMR2_DRH 0x73 /* R : Timer 2 data register (high) */
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#define EZ80_TMR2_RRL 0x72 /* W: Timer 2 reload register (low) */
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#define EZ80_TMR2_RRH 0x73 /* W: Timer 2 reload register (high) */
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#define EZ80_TMR3_CTL 0x74 /* RW: Timer 3 control register */
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#define EZ80_TMR3_IER 0x75 /* RW: Timer 3 interrupt enable register */
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#define EZ80_TMR3_IIR 0x76 /* R : Timer 3 interrupt ID register */
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#define EZ80_TMR3_DRL 0x77 /* R : Timer 3 data register (low) */
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#define EZ80_TMR3_DRH 0x78 /* R : Timer 3 data register (high) */
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#define EZ80_TMR3_RRL 0x77 /* W: Timer 3 reload register (low) */
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#define EZ80_TMR3_RRH 0x78 /* W: Timer 3 reload register (high) */
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#define EZ80_TMR3_CAPCTL 0x7b /* RW: Timer 3 input capture control register */
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#define EZ80_TMR3_CAPAL 0x7c /* R : Timer 3 capture input value A (low) */
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#define EZ80_TMR3_CAPAH 0x7d /* R : Timer 3 capture input value A (high) */
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#define EZ80_TMR3_CAPBL 0x7e /* R : Timer 3 capture input value B (low) */
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#define EZ80_TMR3_CAPBH 0x7f /* R : Timer 3 capture input value B (high) */
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#define EZ80_TMR3_OCCTL1 0x80 /* RW: Timer 3 output compare control register1 */
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#define EZ80_TMR3_OCCTL2 0x81 /* RW: Timer 3 output compare control register2 */
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#define EZ80_TMR3_OC0L 0x82 /* RW: Timer 3 output compare value 0 (low) */
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#define EZ80_TMR3_OC0H 0x83 /* RW: Timer 3 output compare value 0 (high) */
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#define EZ80_TMR3_OC1L 0x84 /* RW: Timer 3 output compare value 1 (low) */
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#define EZ80_TMR3_OC1H 0x85 /* RW: Timer 3 output compare value 1 (high) */
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#define EZ80_TMR3_OC2L 0x86 /* RW: Timer 3 output compare value 2 (low) */
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#define EZ80_TMR3_OC2H 0x87 /* RW: Timer 3 output compare value 2 (high) */
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#define EZ80_TMR3_OC3L 0x88 /* RW: Timer 3 output compare value 3 (low) */
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#define EZ80_TMR3_OC3H 0x89 /* RW: Timer 3 output compare value 3 (high) */
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/* TMR0/1/2/3 CTL Register Bit Definitions **********************************/
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#define EZ80_TMRCTL_BRKSTOP 0x80 /* Bit 7: Stop timer for debug operation */
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#define EZ80_TMRCTL_CLKSEL 0x60 /* Bits 6-5: Timer source */
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# define EZ80_TMRCLKSEL_SYSCLK 0x00 /* 00: System clock divided by prescaler */
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# define EZ80_TMRCLKSEL_RTC 0x20 /* 01: Real time clock input */
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# define EZ80_TMRCLKSEL_ECF 0x40 /* 10: Event count input, falling edge */
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# define EZ80_TMRCLKSEL_ECR 0x60 /* 11: Event count input, rising edge */
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#define EZ80_TMRCTL_CLKDIV 0x18 /* Bits 3-4: System clock divider */
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# define EZ80_TMRCLKDIV_4 0x00 /* 00: 4 */
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# define EZ80_TMRCLKDIV_16 0x08 /* 01: 16 */
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# define EZ80_TMRCLKDIV_64 0x10 /* 10: 64 */
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# define EZ80_TMRCLKDIV_256 0x18 /* 11: 256 */
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#define EZ80_TMRCTL_TIMCONT 0x04 /* Bit 2: Continuous mode */
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#define EZ80_TMRCTL_RLD 0x02 /* Bit 1: Force reload */
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#define EZ80_TMRCTL_TIMEN 0x01 /* Bit 0: Programmable reload timer enabled */
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/* TMR0/1/2/3 IER Register Bit Definitions **********************************/
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/* Bit 7: Reserved */
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#define EZ80_TMRIER_OC3EN 0x40 /* Bit 6: TMR3 OC3 enabled */
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#define EZ80_TMRIER_OC2EN 0x20 /* Bit 5: TMR3 OC2 enabled */
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#define EZ80_TMRIER_OC1EN 0x10 /* Bit 4: TMR3 OC1 enabled */
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#define EZ80_TMRIER_OC0EN 0x08 /* Bit 3: TMR3 OC0 enabled */
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#define EZ80_TMRIER_ICBEN 0x04 /* Bit 2: TMR1/3 capture pin enabled */
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#define EZ80_TMRIER_ICAEN 0x02 /* Bit 1: TMR1/3 capture pin enabled */
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#define EZ80_TMRIER_EOCEN 0x01 /* Bit 0: End of count interrupt enabled */
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/* TMR0/1/2/3 IER Register Bit Definitions **********************************/
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/* Bit 7: Reserved */
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#define EZ80_TMRIIR_OC3 0x40 /* Bit 6: TMR3 OC3 */
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#define EZ80_TMRIIR_OC2 0x20 /* Bit 5: TMR3 OC2 */
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#define EZ80_TMRIIR_OC1 0x10 /* Bit 4: TMR3 OC1 */
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#define EZ80_TMRIIR_OC0 0x08 /* Bit 3: TMR3 OC0 */
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#define EZ80_TMRIIR_ICB 0x04 /* Bit 2: TMR1/3 capture pin */
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#define EZ80_TMRIIR_ICA 0x02 /* Bit 1: TMR1/3 capture pin */
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#define EZ80_TMRIIR_EOC 0x01 /* Bit 0: End of count interrupt */
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/* PWM Registers ************************************************************/
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#define EZ80_PWM_CTL1 0x79
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#define EZ80_PWM_CTL2 0x7a
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#define EZ80_PWM_CTL3 0x7b
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#define EZ80_PWM0R_L 0x7c
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#define EZ80_PWM0R_H 0x7d
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#define EZ80_PWM1R_L 0x7e
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#define EZ80_PWM1R_H 0x7f
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#define EZ80_PWM2R_L 0x80
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#define EZ80_PWM2R_H 0x81
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#define EZ80_PWM3R_L 0x82
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#define EZ80_PWM3R_H 0x83
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#define EZ80_PWM0F_L 0x84
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#define EZ80_PWM0F_H 0x85
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#define EZ80_PWM1F_L 0x86
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#define EZ80_PWM1F_H 0x87
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#define EZ80_PWM2F_L 0x88
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#define EZ80_PWM2F_H 0x89
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#define EZ80_PWM3F_L 0x8a
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#define EZ80_PWM3F_H 0x8b
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/* WDT Registers ************************************************************/
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#define EZ80_WDT_CTL 0x93
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#define EZ80_WDT_RR 0x94
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/* GPIO Registers ***********************************************************/
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#define EZ80_PA_DR 0x96
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#define EZ80_PA_DDR 0x97
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#define EZ80_PA_ALT0 0xa6
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#define EZ80_PA_ALT1 0x98
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#define EZ80_PA_ALT2 0x99
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#define EZ80_PB_DR 0x9a
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#define EZ80_PB_DDR 0x9b
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#define EZ80_PB_ALT0 0xa7
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#define EZ80_PB_ALT1 0x9c
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#define EZ80_PB_ALT2 0x9d
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#define EZ80_PC_DR 0x9e
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#define EZ80_PC_DDR 0x9f
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#define EZ80_PC_ALT0 0xce
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#define EZ80_PC_ALT1 0xa0
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#define EZ80_PC_ALT2 0xa1
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#define EZ80_PD_DR 0xa2
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#define EZ80_PD_DDR 0xa3
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#define EZ80_PD_ALT0 0xcf
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#define EZ80_PD_ALT1 0xa4
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#define EZ80_PD_ALT2 0xa5
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/* CS Registers *************************************************************/
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#define EZ80_CS0_LBR 0xa8
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#define EZ80_CS0_UBR 0xa9
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#define EZ80_CS0_CTL 0xaa
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#define EZ80_CS1_LBR 0xab
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#define EZ80_CS1_UBR 0xac
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#define EZ80_CS1_CTL 0xad
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#define EZ80_CS2_LBR 0xae
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#define EZ80_CS2_UBR 0xaf
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#define EZ80_CS2_CTL 0xb0
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#define EZ80_CS3_LBR 0xb1
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#define EZ80_CS3_UBR 0xb2
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#define EZ80_CS3_CTL 0xb3
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/* RAMCTL reggisters ********************************************************/
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#define EZ80_RAM_CTL 0xb4
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#define EZ80_RAM_CTL0 0xb4
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#define EZ80_RAM_ADDR_U 0xb5
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#define EZ80_MBIST_GPR 0xb6
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#define EZ80_MBIST_EMR 0xb7
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/* RAMCTL bit definitions ***************************************************/
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#define RAMCTL_ERAMEN (1 << 6) /* Bit 7: 1=On chip EMAC SRAM is enabled */
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#define RAMCTL_GPRAMEN (1 << 7) /* Bit 7: 1=On chip GP SRAM is enabled */
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/* SPI Registers ************************************************************/
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#define EZ80_SPI_BRG_L 0xb8
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#define EZ80_SPI_BRG_H 0xb9
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#define EZ80_SPI_CTL 0xba
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#define EZ80_SPI_SR 0xbb
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#define EZ80_SPI_RBR 0xbc
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#define EZ80_SPI_TSR 0xbc
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/* UART Register Offsets ****************************************************/
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/* DLAB=0: */
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#define EZ80_UART_THR 0x00 /* W: UART Transmit holding register */
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#define EZ80_UART_RBR 0x00 /* R : UART Receive buffer register */
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#define EZ80_UART_IER 0x01 /* RW: UART Interrupt enable register */
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/* DLAB=1: */
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#define EZ80_UART_BRG 0x00 /* RW: UART Baud rate generator register */
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#define EZ80_UART_BRGL 0x00 /* RW: UART Baud rate generator register (low) */
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#define EZ80_UART_BRGH 0x01 /* RW: UART Baud rate generator register (high) */
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/* DLAB=N/A: */
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#define EZ80_UART_IIR 0x02 /* R : UART Interrupt identification register */
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#define EZ80_UART_FCTL 0x02 /* W: UART FIFO control register */
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#define EZ80_UART_LCTL 0x03 /* RW: UART Line control register */
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#define EZ80_UART_MCTL 0x04 /* RW: UART Modem control register */
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#define EZ80_UART_LSR 0x05 /* R : UART Line status register */
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#define EZ80_UART_MSR 0x06 /* R : UART Modem status register */
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#define EZ80_UART_SPR 0x07 /* RW: UART Scratchpad register */
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/* UART0/1 Base Register Addresses ******************************************/
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#define EZ80_UART0_BASE 0xc0
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#define EZ80_UART1_BASE 0xd0
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/* UART0/1 IER register bits ************************************************/
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#define EZ80_UARTEIR_INTMASK 0x1f /* Bits 5-7: Reserved */
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#define EZ80_UARTEIR_TCIE 0x10 /* Bit 4: Transmission complete interrupt */
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#define EZ80_UARTEIR_MIIE 0x08 /* Bit 3: Modem status input interrupt */
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#define EZ80_UARTEIR_LSIE 0x04 /* Bit 2: Line status interrupt */
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#define EZ80_UARTEIR_TIE 0x02 /* Bit 1: Transmit interrupt */
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#define EZ80_UARTEIR_RIE 0x01 /* Bit 0: Receive interrupt */
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/* UART0/1 IIR register bits ************************************************/
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#define EZ80_UARTIIR_FSTS 0x80 /* Bit 7: FIFO enable */
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/* Bits 4-6: Reserved */
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#define EZ80_UARTIIR_INSTS 0x0e /* Bits 1-3: Interrupt status code */
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# define EZ80_UARTINSTS_CTO 0x0c /* 110: Character timeout */
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# define EZ80_UARTINSTS_TC 0x0a /* 101: Transmission complete */
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# define EZ80_UARTINSTS_RLS 0x06 /* 011: Receiver line status */
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# define EZ80_UARTINSTS_RDR 0x04 /* 010: Receive data ready or trigger level */
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# define EZ80_UARTINSTS_TBE 0x02 /* 001: Transmisson buffer empty */
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# define EZ80_UARTINSTS_MS 0x00 /* 000: Modem status */
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#define EZ80_UARTIIR_INTBIT 0x01 /* Bit 0: Active interrupt source */
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#define EZ80_UARTIIR_CAUSEMASK 0x0f
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/* UART0/1 FCTL register bits ***********************************************/
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#define EZ80_UARTFCTL_TRIG 0xc0 /* Bits 6-7: UART receive FIFO trigger level */
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# define EZ80_UARTTRIG_1 0x00 /* 00: Receive FIFO trigger level=1 */
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# define EZ80_UARTTRIG_4 0x40 /* 01: Receive FIFO trigger level=4 */
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# define EZ80_UARTTRIG_8 0x80 /* 10: Receive FIFO trigger level=8 */
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# define EZ80_UARTTRIG_14 0xc0 /* 11: Receive FIFO trigger level=14 */
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/* Bit 3-5: Reserved */
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#define EZ80_UARTFCTL_CLRTXF 0x04 /* Bit 2: Transmit enable */
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#define EZ80_UARTFCTL_CLRRXF 0x02 /* Bit 1: Receive enable */
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#define EZ80_UARTFCTL_FIFOEN 0x01 /* Bit 0: Enable receive/transmit FIFOs */
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/* UART0/1 LCTL register bits ***********************************************/
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#define EZ80_UARTLCTL_DLAB 0x80 /* Bit 7: Enable access to baud rate generator */
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#define EZ80_UARTLCTL_SB 0x40 /* Bit 6: Send break */
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#define EZ80_UARTLCTL_FPE 0x20 /* Bit 5: Force parity error */
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#define EZ80_UARTLCTL_EPS 0x10 /* Bit 4: Even parity select */
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#define EZ80_UARTLCTL_PEN 0x08 /* Bit 3: Parity enable */
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#define EZ80_UARTLCTL_2STOP 0x04 /* Bit 2: 2 stop bits */
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#define EZ80_UARTLCTL_CHAR 0x03 /* Bits 0-2: Number of data bits */
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# define EZ80_UARTCHAR_5BITS 0x00 /* 00: 5 data bits */
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# define EZ80_UARTCHAR_6BITS 0x01 /* 01: 6 data bits */
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# define EZ80_UARTCHAR_7BITS 0x02 /* 10: 7 data bits */
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# define EZ80_UARTCHAR_8BITS 0x03 /* 11: 8 data bits */
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#define EZ80_UARTLCTL_MASK 0x3f
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/* UART0/1 MCTL register bits ***********************************************/
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/* Bit 7: Reserved */
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#define EZ80_UARTMCTL_POLARITY 0x40 /* Bit 6: Invert polarity of RxD and TxD */
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#define EZ80_UARTMCTL_MDM 0x20 /* Bit 5: Multi-drop mode enable */
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#define EZ80_UARTMCTL_LOOP 0x10 /* Bit 4: Loopback mode enable */
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#define EZ80_UARTMCTL_OUT2 0x08 /* Bit 3: (loopback mode only) */
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#define EZ80_UARTMCTL_OUT1 0x04 /* Bit 2: (loopback mode only) */
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#define EZ80_UARTMCTL_RTS 0x02 /* Bit 1: Request to send */
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#define EZ80_UARTMCTL_DTR 0x01 /* Bit 0: Data termnal read */
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/* UART0/1 LSR register bits ************************************************/
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#define EZ80_UARTLSR_ERR 0x80 /* Bit 7: Error detected in FIFO */
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#define EZ80_UARTLSR_TEMT 0x40 /* Bit 6: Transmit FIFO empty and idle */
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#define EZ80_UARTLSR_THRE 0x20 /* Bit 5: Transmit FIFO empty */
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#define EZ80_UARTLSR_BI 0x10 /* Bit 4: Break on input */
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#define EZ80_UARTLSR_FE 0x08 /* Bit 3: Framing error */
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#define EZ80_UARTLSR_PE 0x04 /* Bit 2: Parity error */
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#define EZ80_UARTLSR_OE 0x02 /* Bit 1: Overrun error */
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#define EZ80_UARTLSR_DR 0x01 /* Bit 0: Data ready */
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/* UART0/1 MSR register bits ************************************************/
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#define EZ80_UARTMSR_DCD 0x80 /* Bit 7: Data carrier detect */
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#define EZ80_UARTMSR_RI 0x40 /* Bit 6: Ring indicator */
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#define EZ80_UARTMSR_DSR 0x20 /* Bit 5: Data set ready */
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#define EZ80_UARTMSR_CTS 0x10 /* Bit 4: Clear to send */
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#define EZ80_UARTMSR_DDCD 0x08 /* Bit 3: Delta on DCD input */
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#define EZ80_UARTMSR_TERI 0x04 /* Bit 2: Trailing edge change on RI */
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#define EZ80_UARTMSR_DDSR 0x02 /* Bit 1: Delta on DSR input */
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#define EZ80_UARTMSR_DCTS 0x01 /* Bit 0: Delta on CTS input */
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/* IR Registers ************************************************************/
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#define EZ80_IR_CTL 0xbf
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/* I2C Registers ***********************************************************/
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#define EZ80_I2C_SAR 0xc8
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#define EZ80_I2C_XSAR 0xc9
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#define EZ80_I2C_DR 0xca
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#define EZ80_I2C_CTL 0xcb
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#define EZ80_I2C_SR 0xcc
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#define EZ80_I2C_CCR 0xcd
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#define EZ80_I2C_SRR 0xce
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/* CLK Registers ***********************************************************/
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#define EZ80_CLK_PPD1 0xdb
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#define EZ80_CLK_PPD2 0xdc
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/* RTC Registers ***********************************************************/
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#define EZ80_RTC_SEC 0xe0
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#define EZ80_RTC_MIN 0xe1
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#define EZ80_RTC_HRS 0xe2
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#define EZ80_RTC_DOW 0xe3
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#define EZ80_RTC_DOM 0xe4
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#define EZ80_RTC_MON 0xe5
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#define EZ80_RTC_YR 0xe6
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#define EZ80_RTC_CEN 0xe7
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#define EZ80_RTC_ASEC 0xe8
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#define EZ80_RTC_AMIN 0xe9
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#define EZ80_RTC_AHRS 0xea
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#define EZ80_RTC_ADOW 0xeb
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#define EZ80_RTC_ACTRL 0xec
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#define EZ80_RTC_CTRL 0xed
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/* CSBMC Registers *********************************************************/
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#define EZ80_CS0_BMC 0xf0
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#define EZ80_CS1_BMC 0xf1
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#define EZ80_CS2_BMC 0xf2
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#define EZ80_CS3_BMC 0xf3
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/* FLASH Registers *********************************************************/
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#define EZ80_FLASH_KEY 0xf5
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#define EZ80_FLASH_DATA 0xf6
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#define EZ80_FLASH_ADDR_U 0xf7
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#define EZ80_FLASH_CTRL 0xf8
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#define EZ80_FLASH_FDIV 0xf9
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#define EZ80_FLASH_PROT 0xfa
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#define EZ80_FLASH_INTC 0xfb
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#define EZ80_FLASH_PAGE 0xfc
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#define EZ80_FLASH_ROW 0xfd
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#define EZ80_FLASH_COL 0xfe
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#define EZ80_FLASH_PGCTL 0xff
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_Z80_SRC_EZ80_EZ80F91_H */
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