Jukka Laitinen fc41bb7f8a boards/m100pfsevp: Decrease DDR lane temination values to 40 ohm and increase BCLKSCLK_OFFSET ... This fixes problems with DDR training sequence on aries m100pfs board - Set LIBERO_SETTING_RPC_ODT_* to 6, which matches 40 ohm. Originally it was 120 ohm (2) - Set BCLKSCLK_OFFSET value to 5, which matches icicle board setting Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>		2021-12-29 09:36:49 -06:00
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common	boards: move USERMAIN_XX out of INIT_ENTRYPOINT	2021-12-24 08:23:30 -06:00
icicle	arch/risc-v: Refine Toolchain.defs	2021-12-28 00:30:10 -06:00
m100pfsevp	boards/m100pfsevp: Decrease DDR lane temination values to 40 ohm and increase BCLKSCLK_OFFSET	2021-12-29 09:36:49 -06:00