2fc0fbcf7e
commit 89e9d426e91c056e659fccf5e5c4392618f8f777
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Mon Jul 24 16:44:19 2017 -0600
Update some comments
commit 9c5d8a5833350006ed389e898b11c8c8a20e5f4f
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Mon Jul 24 16:15:54 2017 -0600
Spirit: Rename drivers/wireless/spirit/src to lib. Move Spirit network driver out of IEEE802.15.4 into drivers/wireless/spirit/drivers
commit cabc0ec9e6eb558dcb715ab17264383aa0105e7a
Merge: 87b616414a 6bd744c4b3
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Mon Jul 24 15:38:40 2017 -0600
Merge remote-tracking branch 'origin/master' into spirit
commit 87b616414a79c01a71acea78f8258e05325c1996
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Mon Jul 24 15:37:27 2017 -0600
Spirit radio driver is mutating into a standalone network driver.
commit 507798233868a661ae8adad3e3aa117075a7a146
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Mon Jul 24 13:32:08 2017 -0600
Spirit: More radio initialization logic
commit 33af25704ce9ca83d576300d153cfe31cc6d2576
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Mon Jul 24 12:19:14 2017 -0600
Spirit: Beginning of radio initialization logic
commit 97b20014c016e55952a8f9d8f4ae29e2cc555b23
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Mon Jul 24 09:42:06 2017 -0600
Spirit: More initialization logic.
commit 295d8e27824c0417fccea2344b30bb5c93ffbabe
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Sun Jul 23 15:39:53 2017 -0600
Spirit: Add header file containing enumeration of commands.
commit 8a2d9dd8eb9cc70cbcdd1b913fc9022b9c9ec8da
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Sun Jul 23 11:33:50 2017 -0600
Spirit: Add GPIO initialization logic
commit 8b6d80c44f92024c45a6ba63ba1af3fdafe94dc3
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Sun Jul 23 10:07:25 2017 -0600
Spirit: Add interrupt control logic.
commit 423f846fe5c914f92a4bfea4d9d1fa33de1c77a5
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Sat Jul 22 19:06:52 2017 -0600
Spirit: Yet a little more radio initialization logic.
commit 5895b979823e51ddde5ad52e6de66a8ad662e883
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Sat Jul 22 15:36:05 2017 -0600
Spirit: A little more radio initialization logic.
commit 86311ab30aad386203c181c792847dd1d37f9a02
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Sat Jul 22 13:02:32 2017 -0600
Spirit: A miniscule amount of radio initialization logic.
commit ad55e89d5ee12ea1eeea95fcd38ff3da0db4416a
Merge: 90a7666655 f4e46b0da7
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Sat Jul 22 10:56:30 2017 -0600
Merge remote-tracking branch 'origin/master' into spirit
commit 90a766665534b05da0157dbc383cb06a98c86a79
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Sat Jul 22 10:52:52 2017 -0600
Spirit1: A few fixes for a clean build of initial configuration (not much there yet)
commit bbbf04c223230a52a7705a2161128265cfbaa480
Merge: 623d54a7f7 2319ea53a9
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Sat Jul 22 09:53:57 2017 -0600
Merge remote-tracking branch 'origin/master' into spirit
commit 623d54a7f719e9032099f88f38203efee4b80722
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Sat Jul 22 09:43:52 2017 -0600
b-l475e-iot01a: Add a configuration for testing sprit radio.
commit d309d73d9f4665f9d870eb03531f450043d9389d
Merge: 52c3ddfae6 d88dc9b2e5
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Sat Jul 22 09:02:06 2017 -0600
Merge remote-tracking branch 'origin/master' into spirit
commit 52c3ddfae6802e111c2b5cf1207baf21a61dd00b
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Sat Jul 22 08:33:04 2017 -0600
Spirit: Add register definition header file.
commit 8d842ab5e8f9ca653b42f9ee88dc279f06b4fa98
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 21 17:27:03 2017 -0600
b-l475e-iot01a: Add initial, unverified support for the SPSRGF/Spirit1 module.
commit 73d902a1048616fb9c2dd2147cabcd8ee78e19ac
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 21 15:49:43 2017 -0600
Spirit: Fixes to get skeleton IEEE 802.15.4 driver build.
commit ebc5a8387bb94f0cc3827533795f3e4a33207e67
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 21 15:16:29 2017 -0600
Spirit1: Add framework for IEEE 802.15.4 driver. Does not yet build.
commit 52e195a7ae14ddb18bdd56258f4877381d2501ca
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 21 14:02:42 2017 -0600
Spirit: A little more SPI logic.
commit 90048d0c5b8a5af4d81a15d99535c84ed38d8ae9
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 21 11:19:06 2017 -0600
Spirit: Build directories setup. Some initial files added, mostly just to verify build.
commit 8273a381ac1f6bb081b292b5e73226185e9e634c
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Jul 21 08:34:04 2017 -0600
USB composite: Remove references to CDC/ACM and USB MSC from composite logic. They are no longer coupled.
510 lines
18 KiB
C
510 lines
18 KiB
C
/************************************************************************************
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* configs/b-l475e-iot01a/include/b-l475e-iot01a_clock.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __CONFIG_B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK_H
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#define __CONFIG_B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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#if 1
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# define HSI_CLOCK_CONFIG 1 /* HSI-16 clock configuration */
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#elif 0
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/* Make sure you installed one! */
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# define HSE_CLOCK_CONFIG 1 /* HSE with 8 MHz xtal */
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#else
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# define MSI_CLOCK_CONFIG 1 /* MSI @ 4 MHz autotrimmed via LSE */
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#endif
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#if defined(HSI_CLOCK_CONFIG)
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/* The STMicro IoT board supports both HSE and LSE crystals. As shipped, the HSE
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* crystal (X1) is not populated. Therefore the STMicro IoT board will need to run off the
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* 16MHz HSI clock, or the 32khz-synced MSI, unless you install the HSE xtal.
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*
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* System Clock source : PLL (HSI)
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* SYSCLK(Hz) : 80000000 Determined by PLL configuration
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* HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz)
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* AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz)
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* APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz)
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* APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz)
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* HSI Frequency(Hz) : 16000000 (nominal)
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* PLLM : 1 (STM32L4_PLLCFG_PLLM)
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* PLLN : 10 (STM32L4_PLLCFG_PLLN)
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* PLLP : 0 (STM32L4_PLLCFG_PLLP)
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* PLLQ : 0 (STM32L4_PLLCFG_PLLQ)
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* PLLR : 2 (STM32L4_PLLCFG_PLLR)
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* PLLSAI1N : 12
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* PLLSAI1Q : 4
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* Flash Latency(WS) : 4
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* Prefetch Buffer : OFF
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* 48MHz for USB OTG FS, : Doable if required using PLLSAI1 or MSI
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* SDIO and RNG clock
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC (X2)
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* MSI - variable up to 48 MHz, synchronized to LSE
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* HSE - not installed (X1)
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* LSE - 32.768 kHz installed
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*/
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#define STM32L4_HSI_FREQUENCY 16000000ul
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#define STM32L4_LSI_FREQUENCY 32000
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#define STM32L4_LSE_FREQUENCY 32768
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#define STM32L4_BOARD_USEHSI 1
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/* XXX sysclk mux = pllclk */
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/* XXX pll source mux = hsi */
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/* REVISIT: Trimming of the HSI and MSI is not yet supported. */
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/* Main PLL Configuration.
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*
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* Formulae:
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*
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* VCO input frequency = PLL input clock frequency / PLLM, 1 <= PLLM <= 8
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* VCO output frequency = VCO input frequency × PLLN, 8 <= PLLN <= 86, frequency range 64 to 344 MHz
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* PLL output P (SAI3) clock frequency = VCO frequency / PLLP, PLLP = 7, or 17, or 0 to disable
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* PLL output Q (48M1) clock frequency = VCO frequency / PLLQ, PLLQ = 2, 4, 6, or 8, or 0 to disable
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* PLL output R (CLK) clock frequency = VCO frequency / PLLR, PLLR = 2, 4, 6, or 8, or 0 to disable
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*
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* PLL output P is used for SAI
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* PLL output Q is used for OTG FS, SDMMC, RNG
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* PLL output R is used for SYSCLK
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* PLLP = 0 (not used)
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* PLLQ = 0 (not used)
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* PLLR = 2
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* PLLN = 10
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* PLLM = 1
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*
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* We will configure like this
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*
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* PLL source is HSI
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*
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* PLL_REF = STM32L4_HSI_FREQUENCY / PLLM
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* = 16,000,000 / 1
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* = 16,000,000
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*
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* PLL_VCO = PLL_REF * PLLN
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* = 16,000,000 * 10
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* = 160,000,000
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*
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* PLL_CLK = PLL_VCO / PLLR
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* = 160,000,000 / 2 = 80,000,000
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* PLL_48M1 = disabled
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* PLL_SAI3 = disabled
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*
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* ----------------------------------------
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*
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* PLLSAI1 Configuration
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*
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* The clock input and M divider are identical to the main PLL.
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* However the multiplier and postscalers are independent.
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* The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined
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*
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* SAI1VCO input frequency = PLL input clock frequency
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* SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, 8 <= PLLSAI1N <= 86, frequency range 64 to 344 MHz
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* SAI1PLL output P (SAI1) clock frequency = SAI1VCO frequency / PLLSAI1P, PLLP = 7, or 17, or 0 to disable
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* SAI1PLL output Q (48M2) clock frequency = SAI1VCO frequency / PLLSAI1Q, PLLQ = 2, 4, 6, or 8, or 0 to disable
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* SAI1PLL output R (ADC1) clock frequency = SAI1VCO frequency / PLLSAI1R, PLLR = 2, 4, 6, or 8, or 0 to disable
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*
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* We will configure like this
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*
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* PLLSAI1 disabled
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*
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* ----------------------------------------
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*
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* PLLSAI2 Configuration
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*
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* The clock input and M divider are identical to the main PLL.
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* However the multiplier and postscalers are independent.
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* The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined
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*
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* SAI2VCO input frequency = PLL input clock frequency
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* SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, 8 <= PLLSAI1N <= 86, frequency range 64 to 344 MHz
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* SAI2PLL output P (SAI2) clock frequency = SAI2VCO frequency / PLLSAI2P, PLLP = 7, or 17, or 0 to disable
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* SAI2PLL output R (ADC2) clock frequency = SAI2VCO frequency / PLLSAI2R, PLLR = 2, 4, 6, or 8, or 0 to disable
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*
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* We will configure like this
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*
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* PLLSAI2 disabled
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*
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* ----------------------------------------
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*
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* TODO: The STM32L is a low power peripheral and all these clocks should be configurable at runtime.
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*
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* ----------------------------------------
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*
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* TODO These clock sources can be configured in Kconfig (this is not a board feature)
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* USART1
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* USART2
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* USART3
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* UART4
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* UART5
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* LPUART1
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* I2C1
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* I2C2
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* I2C3
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* LPTIM1
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* LPTIM2
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* SAI1
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* SAI2
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* CLK48
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* ADC
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* SWPMI
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* DFSDM
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*/
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/* prescaler common to all PLL inputs; will be 1 (XXX source is implicitly
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as per comment above HSI) */
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#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock via the R
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* output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz
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*
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* XXX NOTE: currently the main PLL is implicitly turned on and is implicitly
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* the system clock; this should be configurable since not all applications may
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* want things done this way.
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*/
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#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10)
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#define STM32L4_PLLCFG_PLLP 0
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#undef STM32L4_PLLCFG_PLLP_ENABLED
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#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2
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#define STM32L4_PLLCFG_PLLQ_ENABLED
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#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
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#define STM32L4_PLLCFG_PLLR_ENABLED
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/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't
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* do that with the main PLL's N value. We set N = 12, and enable
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* the Q output (ultimately for CLK48) with /4. So,
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* 16 MHz / 1 * 12 / 4 = 48 MHz
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*
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* XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the
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* menuconfig, or else all this is a moot point, and the various 48 MHz
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* peripherals will not work (RNG at present). I would suggest removing
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* that option from Kconfig altogether, and simply making it an option
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* that is selected via a #define here, like all these other params.
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*/
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#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12)
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#define STM32L4_PLLSAI1CFG_PLLP 0
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#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4
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#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLR 0
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#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
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/* 'SAIPLL2' is not used in this application */
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#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
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#define STM32L4_PLLSAI2CFG_PLLP 0
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#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI2CFG_PLLR 0
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#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
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#define STM32L4_SYSCLK_FREQUENCY 80000000ul
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/* CLK48 will come from PLLSAI1 (implicitly Q) */
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#define STM32L4_USE_CLK48
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#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
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/* enable the LSE oscillator, used automatically trim the MSI, and for RTC */
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#define STM32L4_USE_LSE 1
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/* AHB clock (HCLK) is SYSCLK (80MHz) */
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#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
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#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */
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#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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/* Timers driven from APB1 will be twice PCLK1 */
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/* REVISIT : this can be configured */
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#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK (80MHz) */
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#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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/* Timers driven from APB2 will be twice PCLK2 */
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/* REVISIT : this can be configured */
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#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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/* REVISIT : this can be configured */
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/* TODO SDMMC */
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#elif defined(HSE_CLOCK_CONFIG)
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/* Use the HSE */
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#define STM32L4_BOARD_USEHSE 1
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/* XXX sysclk mux = pllclk */
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/* XXX pll source mux = hse */
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/* Prescaler common to all PLL inputs */
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#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock */
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#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20)
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#define STM32L4_PLLCFG_PLLP 0
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#undef STM32L4_PLLCFG_PLLP_ENABLED
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#define STM32L4_PLLCFG_PLLQ 0
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#undef STM32L4_PLLCFG_PLLQ_ENABLED
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#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
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#define STM32L4_PLLCFG_PLLR_ENABLED
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/* 'SAIPLL1' is used to generate the 48 MHz clock */
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#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12)
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#define STM32L4_PLLSAI1CFG_PLLP 0
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#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2
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#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLR 0
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#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
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/* 'SAIPLL2' is not used in this application */
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#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
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#define STM32L4_PLLSAI2CFG_PLLP 0
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#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI2CFG_PLLR 0
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#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
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#define STM32L4_SYSCLK_FREQUENCY 80000000ul
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/* Enable CLK48; get it from PLLSAI1 */
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#define STM32L4_USE_CLK48
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#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
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/* Enable LSE (for the RTC) */
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#define STM32L4_USE_LSE 1
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/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
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#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
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#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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/* Configure the APB1 prescaler */
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#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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/* Configure the APB2 prescaler */
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#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#elif defined(MSI_CLOCK_CONFIG)
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/* Use the MSI; frequ = 4 MHz; autotrim from LSE */
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#define STM32L4_BOARD_USEMSI 1
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#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M
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/* XXX sysclk mux = pllclk */
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/* XXX pll source mux = msi */
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/* prescaler common to all PLL inputs */
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#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock */
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#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40)
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#define STM32L4_PLLCFG_PLLP 0
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#undef STM32L4_PLLCFG_PLLP_ENABLED
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#define STM32L4_PLLCFG_PLLQ 0
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#undef STM32L4_PLLCFG_PLLQ_ENABLED
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#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
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#define STM32L4_PLLCFG_PLLR_ENABLED
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/* 'SAIPLL1' is used to generate the 48 MHz clock */
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#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24)
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#define STM32L4_PLLSAI1CFG_PLLP 0
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#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2
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#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLR 0
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#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
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/* 'SAIPLL2' is not used in this application */
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#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
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#define STM32L4_PLLSAI2CFG_PLLP 0
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#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI2CFG_PLLR 0
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#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
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#define STM32L4_SYSCLK_FREQUENCY 80000000ul
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/* Enable CLK48; get it from PLLSAI1 */
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#define STM32L4_USE_CLK48
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#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
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/* Enable LSE (for the RTC) */
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#define STM32L4_USE_LSE 1
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/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
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#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
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#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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/* Configure the APB1 prescaler */
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#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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/* Configure the APB2 prescaler */
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#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#endif
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8,15,16,17 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY
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#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __CONFIG_B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK */
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