ce20211357
Fix typos in these files:
* Documentation/components/drivers/character/foc.rst
* Documentation/guides/cpp_cmake.rst
* Kconfig
* arch/arm/src/imxrt/imxrt_lpspi.c
* arch/arm/src/kinetis/kinetis_spi.c
* arch/arm/src/kl/kl_spi.c
* arch/arm/src/lpc31xx/lpc31_spi.c
* arch/arm/src/nrf52/nrf52_radio.h
* arch/arm/src/s32k1xx/s32k1xx_lpspi.c
* arch/arm/src/stm32/Kconfig
* arch/arm/src/stm32/stm32_adc.c
* arch/arm/src/stm32/stm32_foc.c
* arch/arm/src/stm32/stm32_foc.h
* arch/arm/src/stm32/stm32_pwm.c
* arch/arm/src/stm32/stm32_spi.c
* arch/arm/src/stm32f0l0g0/stm32_spi.c
* arch/arm/src/stm32f7/Kconfig
* arch/arm/src/stm32f7/stm32_spi.c
* arch/arm/src/stm32h7/Kconfig
* arch/arm/src/stm32h7/stm32_allocateheap.c
* arch/arm/src/stm32h7/stm32_fmc.c
* arch/arm/src/stm32h7/stm32_fmc.h
* arch/arm/src/stm32h7/stm32_pwm.c
* arch/arm/src/stm32h7/stm32_qspi.c
* arch/arm/src/stm32h7/stm32_spi.c
* arch/arm/src/stm32l4/stm32l4_pwm.c
* arch/arm/src/stm32l4/stm32l4_spi.c
* arch/arm/src/stm32l5/Kconfig
* arch/arm/src/stm32l5/stm32l5_spi.c
* arch/renesas/src/rx65n/rx65n_dtc.c
* arch/renesas/src/rx65n/rx65n_usbdev.c
* arch/risc-v/src/rv32m1/rv32m1_serial.c
* boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c
* boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c
* boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c
* boards/arm/stm32h7/nucleo-h743zi2/README.txt
* boards/risc-v/rv32m1/rv32m1-vega/README.txt
* boards/sim/sim/sim/scripts/Make.defs
* drivers/1wire/1wire.c
* drivers/1wire/1wire_internal.h
* drivers/lcd/Kconfig
* drivers/syslog/ramlog.c
* fs/fat/Kconfig
* libs/libc/debug/Kconfig
* libs/libc/machine/Kconfig
* libs/libc/stdio/lib_libvsprintf.c
* libs/libc/stdlib/lib_div.c
* libs/libc/stdlib/lib_ldiv.c
* libs/libc/stdlib/lib_lldiv.c
* libs/libdsp/lib_observer.c
243 lines
7.4 KiB
Plaintext
243 lines
7.4 KiB
Plaintext
README
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======
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This README discusses issues unique to NuttX configurations for the
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OPEN ISA RV32M1-VEGA development board featuring the RV32M1 MCU. The
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RV32M1 is a heterogeneous soc including an ARM Cortex-M4 CPU, an ARM
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Cortex-M0+ CPU, a RISC-V RI5CY CPU, and a RISC-V ZERO_RISCY CPU. the
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SOC integrates 1.25 MB flash, 384 KB SRAM, and varieties of peripherals.
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The RV32M1-VEGA board features:
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- On-board OpenSDA Debug Adapter,
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- USB Device Port,
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- FXOS8700CQ Digital Combo Sensor: 3D Accelerometer + 3D Magnetometer,
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- Wirless Abilities: BLE, Generic FSK, and IEEE Std.802.15.4(Thread),
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- ONE user RGB LED,
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- Four user push-buttons,
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- 4 MB external SPI Flash,
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- Micro-SD Card Slot on the backside,
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- Arduino R3 Compatible IO Header.
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Refer to https://open-isa.org for further information about this board.
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Currently NuttX is ported to RV32M1 RI5CY only. RI5CY is RV32IMC RISC-V CPU
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with PULP extensions features:
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- Post-Incrementing load and stores,
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- Multiply-Accumulate extenstions,
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- ALU extensions,
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- Hardware Loops.
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Contents
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========
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- LEDs
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- UARTs
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- Buttons
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- ITCM
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- TSTMR
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LEDs
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====
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The RV32M1-VEGA board has ONE user RGB LED; Only the red part led is used to
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indicate an interrupt request is being serviced.
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SYMBOL Meaning RED* GREEN BLUE
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------------------- ----------------------- ------- ------- -----
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LED_STARTED NuttX has been started OFF OFF OFF
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LED_HEAPALLOCATE Heap has been allocated OFF OFF OFF
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LED_IRQSENABLED Interrupts enabled OFF OFF OFF
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LED_STACKCREATED Idle stack created OFF OFF OFF
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LED_INIRQ In an interrupt** OFF OFF OFF
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LED_SIGNAL In a signal handler*** OFF OFF OFF
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LED_ASSERTION An assertion failed OFF OFF OFF
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LED_PANIC The system has crashed OFF OFF OFF
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LED_CPU Interrupt service ON OFF OFF
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UARTs
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====
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LPUART PINS
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---------------
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LPUART0
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RX PC7, PB25, PA2
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TX PC8, PB26, PA3
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LPUART1
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RX PB2, PC29, PA2, PA25
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TX PB3, PC30, PA3, PA26
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LPUART2
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RX PB11, PB18, PB1
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TX PB12, PB19, PB0
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LPUART3
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RX PB28, PE8, PE29
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TX PB29, PE9, PE30
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Default LPUART Configuration
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--------------------------------
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LPUART0 is enabled in most configurations (see */defconfig). RX and TX are
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configured on pins PC7 and PC8, respectively (see include/board.h). These
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two above pins are connected to onboard Debug Adpater which provides a USB-
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TTL serial channel.
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Buttons
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====
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Four tactile buttons are populated on RV32M1-VEGA Board.
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Buttons PINS Assignment
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---------------
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NAME PIN EXTERNAL-PULLUP
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SW2 PA0 YES
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SW3 PE8 NO
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SW4 PE9 NO
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SW5 PE12 NO
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All these buttons can be used as interrupt and wake up sources while SW2 can
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be an alternative NMI Source.
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ITCM
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====
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A 64KB ITCM is coupled with M4 Cores, RI5CY CPU or ARM Cortex-M4 CPU. If the
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ITCM is selected, Critical Codes including but not limited to Exception Vectors,
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Interrupt Service Routines will be placed in ITCM.
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TSTMR
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====
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TSTMR Module is embedded in RV32M1 to provide system time stamp. It runs off 1MHz
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with a 56-bit counter, and can be adopted to get more accurate delay counting. If
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the Module is selected, a hardware delay method will replace mdealy and udelay,
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the built-in software delay methods.
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TOOLCHAIN
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========
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It is preferable to use OPEN ISA gcc Toolchain to exploit RV32M1 RI5CY capabi-
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lities, though the generic GNU RVG Toolchain can generate binary codes running
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on RV32M1 RI5CY without any problems. To switch generic GNU RVG Toolchain to
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OPEN ISA Toolchain, the following option must be selected:
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Board Selection --->
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[*] Utilize OPEN ISA Toolchain
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Make sure OPEN ISA Toolchain have been installed and be found in PATH.
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ARCHCPUFLAGS
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====
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RI5CY Core supports hardware loop with 6 hardware loop registers assistance,
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these registers could be overwritten when contexts switch. If codes are generated
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by OPEN ISA Toolchain and CONFIG_ARCH_RISCV_INTXCPT_EXTREGS is not less than 6,
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the RI5CY specific architecture flag will be passed to gcc compiler. In that case,
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the 6 hardware loop registers must be saved and restored in interrupt routines with
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the general purpose registers.
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You will see the following lines in Make.defs file:
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ARCHCPURV32IM = -march=rv32imc -mabi=ilp32
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ifeq ($(CONFIG_RV32M1_OPENISA_TOOLCHAIN),y)
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ifdef CONFIG_ARCH_RISCV_INTXCPT_EXTREGS
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ifeq ($(filter 0 1 2 3 4 5 , $(CONFIG_ARCH_RISCV_INTXCPT_EXTREGS)),)
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ARCHCPURV32IM = -march=rv32imcxpulpv2
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endif
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endif
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endif
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ARCHCPUFLAGS = $(ARCHCPURV32IM)
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CONFIG_ARCH_RISV_INTXCPT_EXTREGS could be configured in the following menu:
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System Type --->
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[*] RISC-V Integer Context Extensions
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(6) Number of Extral RISC-V Integer Context Registers
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Program & Debug
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========
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Program
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====
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To program RV32M1, openocd from OPEN ISA and an external jtag adapter are pre-
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requisite. There are 2 tested jtag adapters: Segger Jlink EDU mini and SiPEED
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USB Jtag Adapter. The Segger Jlink EDU mini can connect J55 header on RV32M1-VEGA
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board directly while SiPEED USB Jtag Adpater has to co-operate with an Adapter
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board to setup wires connection.
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Compared to Segger Jlink EDU Mini Adapter, SiPEED USB Jtag Adpater is cheaper but
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not inferior.
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With SiPEED USB Jtag Adapter, some patches must be applied to rv32m1_ri5cy.cfg:
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--- a/rv32m1_ri5cy.cfg
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+++ b/rv32m1_ri5cy.cfg
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@@ -2,7 +2,11 @@ set _WORKAREASIZE 0x2000
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adapter_khz 1000
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-interface jlink
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+interface ftdi
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+ftdi_vid_pid 0x0403 0x6010
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+ftdi_layout_init 0x0508 0x0f1b
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+ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100
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+ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400
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transport select jtag
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set _WORKAREASIZE 0x1000
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------------------------------
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Make sure that RV32M1 boots RI5CY, and you do this ONLY ONCE. Refer to RV32M1-VEGA
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quick start guide for more details.
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Note:
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OPEN ISA Toolchain, rv32m1_ri5cy.cfg contained in RV32M1 SDK, and RV32M1-VEGA
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quick start guide could be found in the following link:
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https://open-isa.org/downloads/
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Debug
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====
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riscv64-unknonw-elf-gdb can not debug RV32M1 RISC-V Cores currently. GDB from
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OPEN ISA Toolchain seems the only option and even can debug elf files generated
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by risc64-unknown-elf-* tools.
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Configuration Sub-directories
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========
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NuttX of all configurations in rv32m1-vega/configs can be compiled by
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the generic GNU RVG Toolchain and OPEN ISA Toolchain.
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buttons
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====
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This configuration is a variant of the NSH configuration used for
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demonstrating the four buttons on RV32M1-VEGA board.
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Example usage of buttons:
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a. Start the buttons daemon:
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nsh> buttons
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b. Press and release SW2, SW3, SW4, SW5 freely, the button pressed
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and released messages will display correspondingly.
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nsh
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====
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This configuration is basic. getprime is included in this configuration to
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determine performance of RV32M1 RI5CY Core.
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nsh-itcm
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====
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This configuration is a variant of the NSH configuration used for
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demonstrating ITCM. When ITCM is selected, RI5CY Exception Vectors and
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Interrupt Service Routines are placed in ITCM. Performance can be calculated
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by getprime, and you might find it deteriorated a litte ironically. The drawback
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may be caused by long jump frequently between ITCM and flash. Besides, an instr-
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uction cache is enabled always after RI5CY resets, and amelioration could not be
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achieved with even ITCM enabled.
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What if codes fullfill the 64KB ITCM ?
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