491 lines
13 KiB
C
491 lines
13 KiB
C
/****************************************************************************
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* arch/x86_64/include/intel64/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_X86_64_INCLUDE_INTEL64_IRQ_H
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#define __ARCH_X86_64_INCLUDE_INTEL64_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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# include <arch/arch.h>
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# include <time.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* ISR and IRQ numbers */
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#define ISR0 0 /* Division by zero exception */
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#define ISR1 1 /* Debug exception */
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#define ISR2 2 /* Non maskable interrupt */
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#define ISR3 3 /* Breakpoint exception */
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#define ISR4 4 /* 'Into detected overflow' */
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#define ISR5 5 /* Out of bounds exception */
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#define ISR6 6 /* Invalid opcode exception */
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#define ISR7 7 /* No coprocessor exception */
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#define ISR8 8 /* Double fault (pushes an error code) */
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#define ISR9 9 /* Coprocessor segment overrun */
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#define ISR10 10 /* Bad TSS (pushes an error code) */
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#define ISR11 11 /* Segment not present (pushes an error code) */
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#define ISR12 12 /* Stack fault (pushes an error code) */
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#define ISR13 13 /* General protection fault (pushes an error code) */
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#define ISR14 14 /* Page fault (pushes an error code) */
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#define ISR15 15 /* Unknown interrupt exception */
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#define ISR16 16 /* Coprocessor fault */
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#define ISR17 17 /* Alignment check exception */
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#define ISR18 18 /* Machine check exception */
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#define ISR19 19 /* SIMD Float-Point Exception*/
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#define ISR20 20 /* Virtualization Exception */
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#define ISR21 21 /* Reserved */
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#define ISR22 22 /* Reserved */
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#define ISR23 23 /* Reserved */
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#define ISR24 24 /* Reserved */
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#define ISR25 25 /* Reserved */
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#define ISR26 26 /* Reserved */
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#define ISR27 27 /* Reserved */
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#define ISR28 28 /* Reserved */
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#define ISR29 29 /* Reserved */
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#define ISR30 30 /* Security Exception */
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#define ISR31 31 /* Reserved */
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#define IRQ0 32 /* System timer (cannot be changed) */
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#define IRQ1 33 /* Keyboard controller (cannot be changed) */
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#define IRQ2 34 /* Cascaded signals from IRQs 8~15 */
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#define IRQ3 35 /* Serial port controller for COM2/4 */
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#define IRQ4 36 /* serial port controller for COM1/3 */
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#define IRQ5 37 /* LPT port 2 or sound card */
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#define IRQ6 38 /* Floppy disk controller */
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#define IRQ7 39 /* LPT port 1 or sound card */
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#define IRQ8 40 /* Real time clock (RTC) */
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#define IRQ9 41 /* Open interrupt/available or SCSI host adapter */
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#define IRQ10 42 /* Open interrupt/available or SCSI or NIC */
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#define IRQ11 43 /* Open interrupt/available or SCSI or NIC */
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#define IRQ12 44 /* Mouse on PS/2 connector */
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#define IRQ13 45 /* Math coprocessor */
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#define IRQ14 46 /* Primary ATA channel */
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#define IRQ15 47 /* Secondary ATA channel */
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#define IRQ_ERROR 51 /* APIC Error */
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#define IRQ_SPURIOUS 0xff /* Spurious Interrupts */
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#define NR_IRQS 48
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/* Common register save structure created by up_saveusercontext() and by
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* ISR/IRQ interrupt processing.
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*/
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#define XCPTCONTEXT_XMM_AREA_SIZE 512
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#define XMMAREA_OFFSET XCPTCONTEXT_XMM_AREA_SIZE / 8
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/* Data segments */
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#define REG_ALIGN (0 + XMMAREA_OFFSET) /* " " "" " " "" " " " " */
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#define REG_FS (1 + XMMAREA_OFFSET) /* " " "" " " "" " " " " */
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#define REG_GS (2 + XMMAREA_OFFSET) /* " " "" " " "" " " " " */
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#define REG_ES (3 + XMMAREA_OFFSET) /* " " "" " " "" " " " " */
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#define REG_DS (4 + XMMAREA_OFFSET) /* Data segment selector */
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/* Remaining regs */
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#define REG_RAX (5 + XMMAREA_OFFSET) /* " " "" " " */
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#define REG_RBX (6 + XMMAREA_OFFSET) /* " " "" " " */
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#define REG_RBP (7 + XMMAREA_OFFSET) /* " " "" " " */
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#define REG_R10 (8 + XMMAREA_OFFSET) /* " " "" " " */
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#define REG_R11 (9 + XMMAREA_OFFSET) /* " " "" " " */
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#define REG_R12 (10 + XMMAREA_OFFSET) /* " " "" " " */
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#define REG_R13 (11 + XMMAREA_OFFSET) /* " " "" " " */
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#define REG_R14 (12 + XMMAREA_OFFSET) /* " " "" " " */
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#define REG_R15 (13 + XMMAREA_OFFSET) /* " " "" " " */
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/* ABI calling convention */
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#define REG_R9 (14 + XMMAREA_OFFSET) /* " " "" " " */
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#define REG_R8 (15 + XMMAREA_OFFSET) /* " " "" " " */
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#define REG_RCX (16 + XMMAREA_OFFSET) /* " " "" " " */
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#define REG_RDX (17 + XMMAREA_OFFSET) /* " " "" " " */
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#define REG_RSI (18 + XMMAREA_OFFSET) /* " " "" " " */
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#define REG_RDI (19 + XMMAREA_OFFSET) /* " " "" " " */
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/* IRQ saved */
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#define REG_ERRCODE (20 + XMMAREA_OFFSET) /* Error code */
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#define REG_RIP (21 + XMMAREA_OFFSET) /* Pushed by process on interrupt processing */
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#define REG_CS (22 + XMMAREA_OFFSET) /* " " "" " " "" " " " " */
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#define REG_RFLAGS (23 + XMMAREA_OFFSET) /* " " "" " " "" " " " " */
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#define REG_RSP (24 + XMMAREA_OFFSET) /* " " "" " " "" " " " " */
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#define REG_SS (25 + XMMAREA_OFFSET) /* " " "" " " "" " " " " */
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/* NOTE 2: This is not really state data. Rather, this is just a convenient
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* way to pass parameters from the interrupt handler to C code.
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*/
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#define XCPTCONTEXT_REGS (26 + XCPTCONTEXT_XMM_AREA_SIZE / 8)
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#define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS + XCPTCONTEXT_XMM_AREA_SIZE)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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enum ioapic_trigger_mode
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{
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TRIGGER_RISING_EDGE = 0,
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TRIGGER_FALLING_EDGE = (1 << 13),
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TRIGGER_LEVEL_ACTIVE_HIGH = 1 << 15,
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TRIGGER_LEVEL_ACTIVE_LOW = (1 << 15) | (1 << 13),
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};
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/* This struct defines the way the registers are stored */
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struct xcptcontext
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{
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/* The following function pointer is non-zero if there are pending signals
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* to be processed.
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*/
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void *sigdeliver; /* Actual type is sig_deliver_t */
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/* These are saved copies of instruction pointer and EFLAGS used during
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* signal processing.
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*/
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uint64_t saved_rip;
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uint64_t saved_rflags;
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uint64_t saved_rsp;
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/* Register save area */
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uint64_t regs[XCPTCONTEXT_REGS] aligned_data(16);
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};
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#endif
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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static inline void setgdt(void *gdt, int size)
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{
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struct gdt_ptr_s gdt_ptr;
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gdt_ptr.limit = size;
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gdt_ptr.base = (uintptr_t)gdt;
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asm volatile ("lgdt %0"::"m"(gdt_ptr):"memory");
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}
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static inline void setidt(void *idt, int size)
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{
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struct idt_ptr_s idt_ptr;
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idt_ptr.limit = size;
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idt_ptr.base = (uintptr_t)idt;
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asm volatile ("lidt %0"::"m"(idt_ptr):"memory");
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}
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static inline uint64_t rdtsc(void)
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{
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uint32_t lo;
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uint32_t hi;
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asm volatile("rdtscp" : "=a" (lo), "=d" (hi)::"memory");
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return (uint64_t)lo | (((uint64_t)hi) << 32);
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}
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static inline uint64_t _rdtsc(void)
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{
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uint32_t lo;
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uint32_t hi;
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asm volatile("rdtsc" : "=a" (lo), "=d" (hi)::"memory");
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return (uint64_t)lo | (((uint64_t)hi) << 32);
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}
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static inline void set_pcid(uint64_t pcid)
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{
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if (pcid < 4095)
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{
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asm volatile("mov %%cr3, %%rbx; andq $-4096, %%rbx; or %0, "
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"%%rbx; mov %%rbx, %%cr3;"
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::"g"(pcid):"memory", "rbx", "rax");
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}
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}
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static inline unsigned long read_msr(unsigned int msr)
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{
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uint32_t low;
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uint32_t high;
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asm volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
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return low | ((unsigned long)high << 32);
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}
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static inline void write_msr(unsigned int msr, unsigned long val)
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{
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asm volatile("wrmsr"
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: /* no output */
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: "c" (msr), "a" (val), "d" (val >> 32)
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: "memory");
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}
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static inline uint64_t read_fsbase(void)
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{
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uint64_t val;
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asm volatile("rdfsbase %0"
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: "=r" (val)
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: /* no output */
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: "memory");
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return val;
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}
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static inline void write_fsbase(unsigned long val)
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{
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asm volatile("wrfsbase %0"
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: /* no output */
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: "r" (val)
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: "memory");
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}
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static inline uint64_t read_gsbase(void)
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{
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uint64_t val;
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asm volatile("rdgsbase %0"
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: "=r" (val)
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: /* no output */
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: "memory");
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return val;
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}
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static inline void write_gsbase(unsigned long val)
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{
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asm volatile("wrgsbase %0"
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: /* no output */
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: "r" (val)
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: "memory");
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}
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/* Return stack pointer */
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static inline uint64_t up_getsp(void)
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{
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uint64_t regval;
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asm volatile(
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"\tmovq %%rsp, %0\n"
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: "=rm" (regval)
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:
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: "memory");
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return regval;
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}
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/* Get segment registers */
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static inline uint32_t up_getds(void)
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{
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uint32_t regval;
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asm volatile(
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"\tmov %%ds, %0\n"
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: "=rm" (regval)
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:
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: "memory");
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return regval;
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}
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static inline uint32_t up_getcs(void)
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{
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uint32_t regval;
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asm volatile(
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"\tmov %%cs, %0\n"
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: "=rm" (regval)
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:
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: "memory");
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return regval;
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}
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static inline uint32_t up_getss(void)
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{
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uint32_t regval;
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asm volatile(
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"\tmov %%ss, %0\n"
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: "=rm" (regval)
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:
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: "memory");
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return regval;
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}
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static inline uint32_t up_getes(void)
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{
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uint32_t regval;
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asm volatile(
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"\tmov %%es, %0\n"
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: "=rm" (regval)
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:
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: "memory");
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return regval;
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}
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static inline uint32_t up_getfs(void)
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{
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uint32_t regval;
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asm volatile(
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"\tmov %%fs, %0\n"
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: "=rm" (regval)
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:
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: "memory");
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return regval;
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}
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static inline uint32_t up_getgs(void)
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{
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uint32_t regval;
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asm volatile(
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"\tmov %%gs, %0\n"
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: "=rm" (regval)
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:
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: "memory");
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return regval;
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}
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/* Name: up_irq_save, up_irq_restore, and friends.
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*
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* NOTE: This function should never be called from application code and,
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* as a general rule unless you really know what you are doing, this
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* function should not be called directly from operation system code either:
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* Typically, the wrapper functions, enter_critical_section() and
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* leave_critical section(), are probably what you really want.
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*/
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/* Get the current FLAGS register contents */
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static inline irqstate_t irqflags()
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{
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irqstate_t flags;
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asm volatile(
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"\tpushfq\n"
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"\tpopq %0\n"
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: "=rm" (flags)
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:
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: "memory");
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return flags;
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}
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/* Get a sample of the FLAGS register, determine if interrupts are disabled.
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* If the X86_FLAGS_IF is cleared by cli, then interrupts are disabled. If
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* if the X86_FLAGS_IF is set by sti, then interrupts are enable.
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*/
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static inline bool up_irq_disabled(irqstate_t flags)
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{
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return ((flags & X86_64_RFLAGS_IF) == 0);
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}
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static inline bool up_irq_enabled(irqstate_t flags)
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{
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return ((flags & X86_64_RFLAGS_IF) != 0);
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}
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/* Disable interrupts unconditionally */
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static inline void up_irq_disable(void)
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{
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asm volatile("cli": : :"memory");
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}
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/* Enable interrupts unconditionally */
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static inline void up_irq_enable(void)
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{
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asm volatile("sti": : :"memory");
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}
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/* Disable interrupts, but return previous interrupt state */
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static inline irqstate_t up_irq_save(void)
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{
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irqstate_t flags = irqflags();
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up_irq_disable();
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return flags;
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}
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/* Conditionally disable interrupts */
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static inline void up_irq_restore(irqstate_t flags)
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{
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if (up_irq_enabled(flags))
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{
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up_irq_enable();
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}
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}
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static inline unsigned int up_apic_cpu_id(void)
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{
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return read_msr(MSR_X2APIC_ID);
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}
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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void up_ioapic_pin_set_vector(unsigned int pin,
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enum ioapic_trigger_mode trigger_mode,
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unsigned int vector);
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_X86_INCLUDE_I486_IRQ_H */
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