Valmantas Palikša bc7566a83f arch/arm/include/armv7-m/syscall.h: ARM EABI specifies that the stack should be aligned by 8 on function calls, inside the function is not required to be aligned by 8. Since these functions call svc, compiler doesn't know that the svc is a function, therefore it does not do any stack management. This change pushes an even number of args to the stack and maintains an 8 byte alignment. I've checked the assembly and it doesn't cause any more overhead that the hand written assembly.		2019-12-16 09:10:08 -06:00
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irq_cmnvector.h	Standardize the width of all comment boxes in header files	2015-10-02 17:42:29 -06:00
irq_lazyfpu.h	Standardize the width of all comment boxes in header files	2015-10-02 17:42:29 -06:00
irq.h	Squashed commit of the following:	2019-04-29 14:52:05 -06:00
nvicpri.h	This commit removes CONFIG_ARCH_INT_DISABLEALL. In the normal course of things, interrupts must occasionally be disabled using the up_irq_save() inline function to prevent contention in use of resources that may be shared between interrupt level and non-interrupt level logic. Now the question arises, if we are using BASEPRI to disable interrupts and have high priority interrupts enabled (CONFIG_ARCH_HIPRI_INTERRUPT=y), do we disable all interrupts except SVCall (we cannot disable SVCall interrupts). Or do we only disable the "normal" interrupts?	2019-08-09 10:52:35 -06:00
spinlock.h	i.MX6 SMP: Inter-CPU data no saved in a non-cacheable region.	2016-11-26 12:04:02 -06:00
syscall.h	arch/arm/include/armv7-m/syscall.h: ARM EABI specifies that the stack should be aligned by 8 on function calls, inside the function is not required to be aligned by 8. Since these functions call svc, compiler doesn't know that the svc is a function, therefore it does not do any stack management. This change pushes an even number of args to the stack and maintains an 8 byte alignment. I've checked the assembly and it doesn't cause any more overhead that the hand written assembly.	2019-12-16 09:10:08 -06:00