66 lines
2.8 KiB
C
66 lines
2.8 KiB
C
/****************************************************************************
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* arch/arm/src/armv7-r/mpcore.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Reference:
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* Cortex™-A9 MPCore, Revision: r4p1, Technical Reference Manual, ARM DDI
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* 0407I (ID091612).
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*/
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#ifndef __ARCH_ARM_SRC_ARMV7_R_MPCORE_H
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#define __ARCH_ARM_SRC_ARMV7_R_MPCORE_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "chip.h" /* For CHIP_MPCORE_VBASE */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* MPCore registers are memory mapped and accessed through a processor
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* specific private address space via the SCU. The Cortex-A9 MCU chip.h
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* header file must provide the definition CHIP_MPCORE_VBASE to access this
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* the registers in this memory region.
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*/
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/* Peripheral Base Offsets **************************************************/
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#define MPCORE_SCU_OFFSET 0x0000 /* 0x0000-0x00fc SCU registers */
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#define MPCORE_ICC_OFFSET 0x2000 /* 0x0000-0x00FC Interrupt controller interface */
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#define MPCORE_GTM_OFFSET 0x0200 /* 0x0200-0x02ff Global timer */
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/* 0x0300-0x05ff Reserved */
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#define MPCORE_PTM_OFFSET 0x0600 /* 0x0600-0x06ff Private timers and watchdogs */
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/* 0x0700-0x07ff Reserved */
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#define MPCORE_ICD_OFFSET 0x1000 /* 0x1000-0x1fff Interrupt Distributor */
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/* Peripheral Base Addresses ************************************************/
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#define MPCORE_SCU_VBASE (CHIP_MPCORE_VBASE+MPCORE_SCU_OFFSET)
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#define MPCORE_ICC_VBASE (CHIP_MPCORE_VBASE+MPCORE_ICC_OFFSET)
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#define MPCORE_GTM_VBASE (CHIP_MPCORE_VBASE+MPCORE_GTM_OFFSET)
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#define MPCORE_PTM_VBASE (CHIP_MPCORE_VBASE+MPCORE_PTM_OFFSET)
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#define MPCORE_ICD_VBASE (CHIP_MPCORE_VBASE+MPCORE_ICD_OFFSET)
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#endif /* __ARCH_ARM_SRC_ARMV7_R_MPCORE_H */
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