3a262416d6
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5146 42af7a65-404d-4744-a932-0658087f49c3
128 lines
4.9 KiB
C
128 lines
4.9 KiB
C
/************************************************************************
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* arch/arm/src/lpc31xx/lpc31_fdcndx.c
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*
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* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
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* - lpc313x.cdl.drivers.zip example driver code
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************/
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/************************************************************************
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* Included Files
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************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include "up_arch.h"
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#include "lpc31_cgudrvr.h"
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/************************************************************************
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* Pre-processor Definitions
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************************************************************************/
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/* The select register in the ESR registers vary in width from 1-3 bits.
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* Below is a macro to select the widest case (which is OK because the
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* undefined bits will be read as zero). Within the field, bits 0-7 to
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* indicate the offset from the base FDC index.
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*/
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#define CGU_ESRSEL(n) (((n)>>1)&7)
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/************************************************************************
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* Private Data
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************************************************************************/
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static const uint8_t g_fdcbase[CGU_NDOMAINS] =
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{
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FRACDIV_BASE0_LOW, /* Domain 0: SYS_BASE */
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FRACDIV_BASE1_LOW, /* Domain 1: AHB0APB0_BASE */
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FRACDIV_BASE2_LOW, /* Domain 2: AHB0APB1_BASE */
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FRACDIV_BASE3_LOW, /* Domain 3: AHB0APB2_BASE */
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FRACDIV_BASE4_LOW, /* Domain 4: AHB0APB3_BASE */
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FRACDIV_BASE5_LOW, /* Domain 5: PCM_BASE */
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FRACDIV_BASE6_LOW, /* Domain 6: UART_BASE */
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FRACDIV_BASE7_LOW, /* Domain 7: CLK1024FS_BASE */
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0, /* Domain 8: BCK0_BASE (no ESR register) */
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0, /* Domain 9: BCK1_BASE (no ESR register) */
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FRACDIV_BASE10_LOW, /* Domain 10: SPI_BASE */
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0, /* Domain 11: SYSCLKO_BASE (no ESR register) */
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};
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/************************************************************************
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* Private Functions
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************************************************************************/
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/************************************************************************
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* Public Functions
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************************************************************************/
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/************************************************************************
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* Name: lpc31_fdcndx
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*
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* Description:
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* Given a clock ID and its domain ID, return the index of the
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* corresponding fractional divider register (or FDCNDX_INVALID if
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* there is no fractional divider associated with this clock).
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*
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************************************************************************/
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int lpc31_fdcndx(enum lpc31_clockid_e clkid, enum lpc31_domainid_e dmnid)
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{
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int esrndx;
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int fdcndx = FDCNDX_INVALID;
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/* Check if there is an ESR register associate with this clock ID */
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esrndx = lpc31_esrndx(clkid);
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if (esrndx != ESRNDX_INVALID)
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{
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/* Read the clock's ESR to get the fractional divider */
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uint32_t regval = getreg32(LPC31_CGU_ESR(esrndx));
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/* Check if any fractional divider is enabled for this clock. */
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if ((regval & CGU_ESR_ESREN) != 0)
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{
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/* Yes.. The FDC index is an offset from this fractional
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* divider base for this domain.
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*/
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fdcndx = CGU_ESRSEL(regval) + (int)g_fdcbase[dmnid];
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}
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}
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return fdcndx;
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}
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