b128ce334f
OpenSBI may be compiled as an external library. OpenSBI commit d249d65
(Dec. 11, 2021) needs to be reverted as it causes memcpy / memcmp to
end up in the wrong section. That issue has yet no known workaround.
OpenSBI may be lauched from the hart0 (e51). It will start the U-Boot
and eventually the Linux kernel on harts 1-4.
OpenSBI, once initialized properly, will trap and handle illegal
instructions (for example, CSR time) and unaligned address accesses
among other things.
Due to size size limitations for the mpfs eNVM area where the NuttX
is located, we actually set up the OpenSBI on its own section which
is in the bottom of the DDR memory. Special care must be taken so that
the kernel doesn't override the OpenSBI. For example, the Linux device
tree may reserve some space from the beginning:
opensbi_reserved: opensbi@80000000 {
reg = <0x80000000 0x200000>;
label = "opensbi-reserved";
};
The resulting nuttx.bin file is very large, but objcopy is used to
create the final binary images for the regions (eNVM and DDR) using
the nuttx elf file.
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
187 lines
4.1 KiB
Plaintext
187 lines
4.1 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_RISCV
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comment "RISC-V Options"
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choice
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prompt "RISC-V chip selection"
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default ARCH_CHIP_RISCV_CUSTOM
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config ARCH_CHIP_FE310
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bool "SiFive FE310"
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select ARCH_RV32IM
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---help---
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SiFive FE310 processor (E31 RISC-V Core with MAC extensions).
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config ARCH_CHIP_K210
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bool "Kendryte K210"
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select ARCH_RV64GC
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select ARCH_HAVE_MPU
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_MULTICPU
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---help---
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Kendryte K210 processor (RISC-V 64bit core with GC extensions)
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config ARCH_CHIP_LITEX
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bool "Enjoy Digital LITEX VEXRISCV"
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select ARCH_RV32IM
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---help---
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Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA).
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config ARCH_CHIP_BL602
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bool "BouffaloLab BL602"
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select ARCH_RV32IM
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select ARCH_HAVE_FPU
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select ARCH_HAVE_RESET
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---help---
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BouffaloLab BL602(rv32imfc)
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config ARCH_CHIP_ESP32C3
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bool "Espressif ESP32-C3"
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select ARCH_RV32IM
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select RV32IM_HW_MULDIV
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select ARCH_VECNOTIRQ
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select ARCH_HAVE_RESET
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select LIBC_ARCH_ATOMIC
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select LIBC_ARCH_MEMSET
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select LIBC_ARCH_MEMCPY
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select LIBC_ARCH_MEMMOVE
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select LIBC_ARCH_MEMCMP
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select LIBC_ARCH_MEMCHR
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select LIBC_ARCH_STRCPY
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select LIBC_ARCH_STRCHR
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select LIBC_ARCH_STRCMP
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select LIBC_ARCH_STRLCPY
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select LIBC_ARCH_STRNCPY
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select LIBC_ARCH_STRLEN
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select LIBC_ARCH_STRNLEN
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select ARCH_HAVE_TEXT_HEAP
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select ARCH_HAVE_BOOTLOADER
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---help---
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Espressif ESP32-C3 (RV32IMC).
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config ARCH_CHIP_C906
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bool "THEAD C906"
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select ARCH_RV64GC
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select ARCH_HAVE_MPU
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---help---
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THEAD C906 processor (RISC-V 64bit core with GCVX extensions).
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config ARCH_CHIP_MPFS
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bool "MicroChip Polarfire (MPFS)"
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select ARCH_RV64GC
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select ARCH_HAVE_MPU
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select ARCH_HAVE_RESET
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select ARCH_HAVE_SPI_CS_CONTROL
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select ARCH_HAVE_PWM_MULTICHAN
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---help---
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MicroChip Polarfire processor (RISC-V 64bit core with GCVX extensions).
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config ARCH_CHIP_RV32M1
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bool "NXP RV32M1"
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select ARCH_RV32IM
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---help---
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NXP RV32M1 processor (RISC-V Core with PULP extensions).
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config ARCH_CHIP_QEMU_RV32
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bool "QEMU RV32"
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select ARCH_RV32IM
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---help---
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QEMU Generic RV32 processor
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config ARCH_CHIP_RISCV_CUSTOM
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bool "Custom RISC-V chip"
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select ARCH_CHIP_CUSTOM
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---help---
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Select this option if there is no directory for the chip under arch/risc-v/src/.
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endchoice
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config ARCH_RV32I
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bool
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default n
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select ARCH_HAVE_SETJMP
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config ARCH_RV32IM
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bool
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default n
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select ARCH_HAVE_SETJMP
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config ARCH_RV64GC
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bool
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default n
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select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF
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select ARCH_HAVE_SETJMP
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config ARCH_FAMILY
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string
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default "rv32im" if ARCH_RV32IM
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default "rv64gc" if ARCH_RV64GC
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config ARCH_CHIP
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string
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default "fe310" if ARCH_CHIP_FE310
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default "k210" if ARCH_CHIP_K210
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default "litex" if ARCH_CHIP_LITEX
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default "bl602" if ARCH_CHIP_BL602
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default "esp32c3" if ARCH_CHIP_ESP32C3
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default "c906" if ARCH_CHIP_C906
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default "mpfs" if ARCH_CHIP_MPFS
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default "rv32m1" if ARCH_CHIP_RV32M1
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default "qemu-rv32" if ARCH_CHIP_QEMU_RV32
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config ARCH_RISCV_INTXCPT_EXTENSIONS
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bool "RISC-V Integer Context Extensions"
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default n
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---help---
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RISC-V could be customized with extensions. Some Integer Context
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Registers have to be saved and restored when Contexts switch.
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if ARCH_RISCV_INTXCPT_EXTENSIONS
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config ARCH_RISCV_INTXCPT_EXTREGS
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int "Number of Extral RISC-V Integer Context Registers"
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default 0
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endif
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source "arch/risc-v/src/opensbi/Kconfig"
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if ARCH_RV32IM
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source "arch/risc-v/src/rv32im/Kconfig"
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endif
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if ARCH_RV64GC
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source "arch/risc-v/src/rv64gc/Kconfig"
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endif
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if ARCH_CHIP_FE310
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source "arch/risc-v/src/fe310/Kconfig"
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endif
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if ARCH_CHIP_K210
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source "arch/risc-v/src/k210/Kconfig"
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endif
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if ARCH_CHIP_LITEX
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source "arch/risc-v/src/litex/Kconfig"
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endif
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if ARCH_CHIP_BL602
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source "arch/risc-v/src/bl602/Kconfig"
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endif
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if ARCH_CHIP_ESP32C3
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source "arch/risc-v/src/esp32c3/Kconfig"
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endif
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if ARCH_CHIP_C906
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source "arch/risc-v/src/c906/Kconfig"
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endif
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if ARCH_CHIP_MPFS
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source "arch/risc-v/src/mpfs/Kconfig"
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endif
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if ARCH_CHIP_RV32M1
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source "arch/risc-v/src/rv32m1/Kconfig"
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endif
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if ARCH_CHIP_QEMU_RV32
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source "arch/risc-v/src/qemu-rv32/Kconfig"
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endif
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endif
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