996b9377a7
Add support for tricore TC397 1. Porting based on AURIX TC397 KIT_A2G_TC397_5V_TFT evaluation board https://www.infineon.com/cms/en/product/evaluation-boards/kit_a2g_tc397_5v_tft/ 2. In order to avoid license and coding style issues, The chip-level code still uses the implementation of AURIX Development Studio SDK. The SDK package will be downloaded as a third-party package during compilation: https://github.com/anchao/tc397_sdk 3. Single core only, SMP implementation will be provided in the future. 4. Implemented the basic System Timer, ASCLIN UART driver. 5. Only the Tasking tool chain is supported (ctc/ltc, license maybe required) 6. 'ostest' can be completed on the TC397 development board. How to run? 1. Setup the tasking toolchain and license $ export TSK_LICENSE_KEY_SW160800=d22f-7473-ff5d-1b70 $ export TSK_LICENSE_SERVER=192.168.36.12:9090 2. Build nuttx ELF $ ./tools/configure.sh tc397/nsh $ make -j ... artc I800: creating archive libc_fpu.a LD: nuttx 3. Switch to windows PC, setup AURIX-studio to Debugger Launcher 4. Replace runing ELF to nuttx, and re-download ELF Signed-off-by: chao an <anchao@lixiang.com>
141 lines
4.5 KiB
C
141 lines
4.5 KiB
C
/****************************************************************************
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* arch/tricore/include/tc3xx/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_TRICORE_INCLUDE_TC3XX_IRQ_H
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#define __ARCH_TRICORE_INCLUDE_TC3XX_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Upper CSA */
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#define REG_UPCXI 0
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#define REG_PSW 1
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#define REG_A10 2
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#define REG_UA11 3
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#define REG_D8 4
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#define REG_D9 5
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#define REG_D10 6
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#define REG_D11 7
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#define REG_A12 8
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#define REG_A13 9
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#define REG_A14 10
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#define REG_A15 11
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#define REG_D12 12
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#define REG_D13 13
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#define REG_D14 14
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#define REG_D15 15
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/* Lower CSA */
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#define REG_LPCXI 0
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#define REG_LA11 1
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#define REG_A2 2
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#define REG_A3 3
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#define REG_D0 4
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#define REG_D1 5
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#define REG_D2 6
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#define REG_D3 7
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#define REG_A4 8
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#define REG_A5 9
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#define REG_A6 10
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#define REG_A7 11
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#define REG_D4 12
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#define REG_D5 13
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#define REG_D6 14
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#define REG_D7 15
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#define REG_RA REG_UA11
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#define REG_SP REG_A10
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#define REG_UPC REG_UA11
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#define REG_LPC REG_LA11
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#define TC_CONTEXT_REGS (16)
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#define XCPTCONTEXT_REGS (TC_CONTEXT_REGS)
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#define XCPTCONTEXT_SIZE (sizeof(void *) * TC_CONTEXT_REGS)
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#define NR_IRQS (255)
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/* PSW: Program Status Word Register */
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#define PSW_CDE (1 << 7) /* Bits 7: Call Depth Count Enable */
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#define PSW_IS (1 << 9) /* Bits 9: Interrupt Stack Control */
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#define PSW_IO (10) /* Bits 10-11: Access Privilege Level Control (I/O Privilege) */
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# define PSW_IO_USER0 (0 << PSW_IO)
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# define PSW_IO_USER1 (1 << PSW_IO)
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# define PSW_IO_SUPERVISOR (2 << PSW_IO)
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/* PCXI: Previous Context Information and Pointer Register */
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#define PCXI_UL (1 << 20) /* Bits 20: Upper or Lower Context Tag */
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#define PCXI_PIE (1 << 21) /* Bits 21: Previous Interrupt Enable */
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/* FCX: Free CSA List Head Pointer Register */
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#define FCX_FCXO (0) /* Bits 0-15: FCX Offset Address */
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#define FCX_FCXS (16) /* Bits 16-19: FCX Segment Address */
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#define FCX_FCXO_MASK (0xffff << FCX_FCXO)
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#define FCX_FCXS_MASK (0xf << FCX_FCXS)
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#define FCX_FREE (FCX_FCXS_MASK | FCX_FCXO_MASK) /* Free CSA manipulation */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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struct xcptcontext
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{
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/* The following function pointer is non-zero if there are pending signals
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* to be processed.
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*/
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void *sigdeliver; /* Actual type is sig_deliver_t */
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/* These are saved copies of the context used during
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* signal processing.
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*/
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uintptr_t *saved_regs;
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/* Register save area with XCPTCONTEXT_SIZE, only valid when:
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* 1.The task isn't running or
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* 2.The task is interrupted
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* otherwise task is running, and regs contain the stale value.
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*/
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uintptr_t *regs;
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_TRICORE_INCLUDE_TC3XX_IRQ_H */
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