129 lines
4.5 KiB
C
129 lines
4.5 KiB
C
/****************************************************************************
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* boards/arm/sam34/sam4cmp-db/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_SAM34_SAM4CMP_DB_INCLUDE_BOARD_H
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#define __BOARDS_ARM_SAM34_SAM4CMP_DB_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* After power-on reset, the sam3u device is running on a 4MHz internal RC.
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* These definitions will configure clocking with MCK = 48MHz, PLLA = 96,
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* and CPU=120MHz.
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*/
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/* Main oscillator register settings */
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#define BOARD_CKGR_MOR_MOSCXTST (63 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
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/* PLLA configuration:
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*
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* Source: 12MHz crystall at 12MHz
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* PLLdiv: 10
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* PLLmul: 1 (bypassed)
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* Fpll: (12MHz * 10) / 1 = 120MHz
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*/
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#define BOARD_MAINOSC_FREQUENCY (8192000)
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#define BOARD_CKGR_PLLAR_MUL (9 << PMC_CKGR_PLLAR_MUL_SHIFT)
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#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
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#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
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#define BOARD_PLLA_FREQUENCY (10*BOARD_MAINOSC_FREQUENCY)
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/* PLLB configuration
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*
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* Source: MAIN clock (i.e. 8.192MHz)
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* PLLdiv: 4
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* PLLmul: 45
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* Fpll: (8.192MHz * (44+1) / 4 = 92.120 MHz
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*/
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#define BOARD_CKGR_PLLBR_SRCB (0 << PMC_CKGR_PLLBR_SRCB_SHIFT)
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#define BOARD_CKGR_PLLBR_DIV (4 << PMC_CKGR_PLLBR_DIV_SHIFT)
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#define BOARD_CKGR_PLLBR_MUL (44 << PMC_CKGR_PLLBR_MUL_SHIFT)
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#define BOARD_CKGR_PLLBR_COUNT (63 << PMC_CKGR_PLLBR_COUNT_SHIFT)
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#define BOARD_PLLB_FREQUENCY (92160000)
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/* PMC master clock register settings */
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#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLB
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#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1
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#define BOARD_MCK_FREQUENCY (BOARD_PLLB_FREQUENCY/1)
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#define BOARD_CPU_FREQUENCY (BOARD_PLLB_FREQUENCY/1)
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/* USB UTMI PLL start-up time */
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#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT)
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/* FLASH wait states:
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*
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* DC Characteristics
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*
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* Parameter Min Typ Max
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* ---------------------- ----- ----- ----
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* Vddcore DC Supply Core 1.08V 1.2V 1.32V
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* Vvddio DC Supply I/Os 1.62V 3.3V 3.6V
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*
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* Wait Maximum
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* Vddcore Vvddio States Frequency (MHz)
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* ------- ---------- ------ ---------------
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* 1.08V 1.62-3.6V 0 16
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* " " " "-" " 1 33
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* " " " "-" " 2 50
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* " " " "-" " 3 67
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* " " " "-" " 4 84
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* " " " "-" " 5 100
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* 1.08V 2.7-3.6V 0 20
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* " " " "-" " 1 40
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* " " " "-" " 2 60
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* " " " "-" " 3 80
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* " " " "-" " 4 100
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* 1.2V 1.62-3.6V 0 17
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* " " " "-" " 1 34
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* " " " "-" " 2 52
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* " " " "-" " 3 69
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* " " " "-" " 4 87
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* " " " "-" " 5 104
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* " " " "-" " 6 121
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* 1.2V 2.7-3.6V 0 21
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* " " " "-" " 1 42
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* " " " "-" " 2 63
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* " " " "-" " 3 84
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* " " " "-" " 4 105
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* " " " "-" " 5 123 << SELECTION
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*/
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#define BOARD_FWS 5
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#endif /* __BOARDS_ARM_SAM34_SAM4CMP_DB_INCLUDE_BOARD_H */
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