34bfa2f7ba
Adds a platform specific implementation for tickless schedular operation. This includes: - Tickless operation for vexriscv cores. - Tickless operation for vexriscv-smp cores. - Ticked operation for vexriscv-smp cores. Ticked operation for vexriscv core has been refactored. Additional default configuration added to demonstrate operation. Both tickless and ticked options use Litex timer0 for scheduling intervals. This is significantly faster than interfaceing with the risc-v mtimer through opensbi.
452 lines
10 KiB
Plaintext
452 lines
10 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_RISCV
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comment "RISC-V Options"
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choice
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prompt "RISC-V chip selection"
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default ARCH_CHIP_RISCV_CUSTOM
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config ARCH_CHIP_FE310
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bool "SiFive FE310"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ONESHOT
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select ALARM_ARCH
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---help---
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SiFive FE310 processor (E31 RISC-V Core with MAC extensions).
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config ARCH_CHIP_K210
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bool "Kendryte K210"
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select ARCH_RV64
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU if !K210_WITH_QEMU
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select ARCH_HAVE_DPFPU if !K210_WITH_QEMU
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select ARCH_HAVE_MPU
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_MULTICPU
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select ARCH_HAVE_MISALIGN_EXCEPTION
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select ONESHOT
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select ALARM_ARCH
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---help---
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Kendryte K210 processor (RISC-V 64bit core with GC extensions)
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config ARCH_CHIP_LITEX
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bool "Enjoy Digital LITEX VEXRISCV"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_DCACHE
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select ARCH_HAVE_TICKLESS
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---help---
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Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA).
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config ARCH_CHIP_BL602
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bool "BouffaloLab BL602"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU
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select ARCH_HAVE_RESET
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select ARCH_HAVE_MISALIGN_EXCEPTION
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select ONESHOT
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select ALARM_ARCH
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---help---
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BouffaloLab BL602(rv32imfc)
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config ARCH_CHIP_ESP32C3
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bool "Espressif ESP32-C3"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_C
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select ARCH_VECNOTIRQ
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select ARCH_HAVE_MPU
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select ARCH_HAVE_RESET
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select LIBC_ARCH_ATOMIC
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select LIBC_ARCH_MEMCPY
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select LIBC_ARCH_MEMCHR
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select LIBC_ARCH_MEMCMP
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select LIBC_ARCH_MEMMOVE
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select LIBC_ARCH_MEMSET
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select LIBC_ARCH_STRCHR
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select LIBC_ARCH_STRCMP
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select LIBC_ARCH_STRCPY
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select LIBC_ARCH_STRLCPY
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select LIBC_ARCH_STRNCPY
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select LIBC_ARCH_STRLEN
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select LIBC_ARCH_STRNLEN
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select ARCH_HAVE_TEXT_HEAP
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select ARCH_HAVE_BOOTLOADER
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select ARCH_HAVE_PERF_EVENTS
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---help---
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Espressif ESP32-C3 (RV32IMC).
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config ARCH_CHIP_ESP32C6
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bool "Espressif ESP32-C6"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_VECNOTIRQ
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select ARCH_HAVE_RESET
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select LIBC_ARCH_MEMCPY
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select LIBC_ARCH_MEMCHR
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select LIBC_ARCH_MEMCMP
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select LIBC_ARCH_MEMMOVE
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select LIBC_ARCH_MEMSET
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select LIBC_ARCH_STRCHR
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select LIBC_ARCH_STRCMP
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select LIBC_ARCH_STRCPY
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select LIBC_ARCH_STRLCPY
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select LIBC_ARCH_STRNCPY
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select LIBC_ARCH_STRLEN
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select LIBC_ARCH_STRNLEN
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---help---
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Espressif ESP32-C6 (RV32IMAC).
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config ARCH_CHIP_ESPRESSIF
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bool "Espressif ESP32 family"
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---help---
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Family of RISC-V based microcontrollers from Espressif Systems.
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config ARCH_CHIP_C906
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bool "THEAD C906"
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select ARCH_RV64
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_MPU
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select ONESHOT
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select ALARM_ARCH
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---help---
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THEAD C906 processor (RISC-V 64bit core with GCVX extensions).
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config ARCH_CHIP_MPFS
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bool "MicroChip Polarfire (MPFS)"
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select ARCH_RV64
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MMU
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select ARCH_MMU_TYPE_SV39
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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select ARCH_HAVE_RESET
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select ARCH_HAVE_SPI_CS_CONTROL
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select ARCH_HAVE_PWM_MULTICHAN
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select ARCH_HAVE_S_MODE
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select PMP_HAS_LIMITED_FEATURES
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select ONESHOT
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select ALARM_ARCH
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---help---
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MicroChip Polarfire processor (RISC-V 64bit core with GCVX extensions).
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config ARCH_CHIP_RV32M1
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bool "NXP RV32M1"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_C
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---help---
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NXP RV32M1 processor (RISC-V Core with PULP extensions).
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config ARCH_CHIP_QEMU_RV
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bool "QEMU RV"
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_MULTICPU
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MMU
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select ARCH_MMU_TYPE_SV39 if ARCH_CHIP_QEMU_RV64
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select ARCH_MMU_TYPE_SV32 if ARCH_CHIP_QEMU_RV32
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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select ARCH_HAVE_S_MODE
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select ONESHOT
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select ALARM_ARCH
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---help---
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QEMU Generic RV32/RV64 processor
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config ARCH_CHIP_HPM6750
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bool "Hpmicro HPM6750"
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select ARCH_RV32
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ONESHOT
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select ALARM_ARCH
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---help---
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Hpmicro HPM6750 processor (D45 RISC-V Core with MAC extensions).
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config ARCH_CHIP_JH7110
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bool "StarFive JH7110"
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select ARCH_RV64
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select ARCH_RV_ISA_M
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select ARCH_RV_ISA_A
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select ARCH_RV_ISA_C
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU
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select ARCH_HAVE_MULTICPU
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MMU
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select ARCH_MMU_TYPE_SV39
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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select ARCH_HAVE_S_MODE
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select ONESHOT
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select ALARM_ARCH
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---help---
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StarFive JH7110 SoC.
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config ARCH_CHIP_RISCV_CUSTOM
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bool "Custom RISC-V chip"
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select ARCH_CHIP_CUSTOM
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---help---
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Select this option if there is no directory for the chip under arch/risc-v/src/.
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endchoice
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config ARCH_RV32
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bool
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default n
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config ARCH_RV64
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bool
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default n
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select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF
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config ARCH_RV_ISA_M
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bool
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default n
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config ARCH_RV_ISA_A
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bool
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default n
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select ARCH_HAVE_TESTSET
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config ARCH_RV_ISA_C
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bool
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default n
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config ARCH_FAMILY
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string
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default "rv32" if ARCH_RV32
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default "rv64" if ARCH_RV64
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config ARCH_CHIP
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string
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default "fe310" if ARCH_CHIP_FE310
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default "k210" if ARCH_CHIP_K210
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default "litex" if ARCH_CHIP_LITEX
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default "bl602" if ARCH_CHIP_BL602
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default "esp32c3" if ARCH_CHIP_ESP32C3
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default "esp32c6" if ARCH_CHIP_ESP32C6
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default "espressif" if ARCH_CHIP_ESPRESSIF
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default "c906" if ARCH_CHIP_C906
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default "mpfs" if ARCH_CHIP_MPFS
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default "rv32m1" if ARCH_CHIP_RV32M1
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default "qemu-rv" if ARCH_CHIP_QEMU_RV
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default "hpm6750" if ARCH_CHIP_HPM6750
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default "jh7110" if ARCH_CHIP_JH7110
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config ARCH_RISCV_INTXCPT_EXTENSIONS
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bool "RISC-V Integer Context Extensions"
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default n
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depends on RV32M1_OPENISA_TOOLCHAIN
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---help---
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RISC-V could be customized with extensions. Some Integer Context
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Registers have to be saved and restored when Contexts switch.
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if ARCH_RISCV_INTXCPT_EXTENSIONS
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config ARCH_RISCV_INTXCPT_EXTREGS
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int "Number of Extral RISC-V Integer Context Registers"
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default 0
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endif
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config ARCH_MMU_TYPE_SV39
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bool
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default n
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config ARCH_MMU_TYPE_SV32
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bool
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default n
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config ARCH_HAVE_S_MODE
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bool
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default n
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config ARCH_HAVE_MISALIGN_EXCEPTION
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bool
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default n
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---help---
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The chip will raise a exception while misaligned memory access.
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config RISCV_MISALIGNED_HANDLER
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bool "Software misaligned memory access handler"
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depends on ARCH_HAVE_MISALIGN_EXCEPTION
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default y
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# Option to run NuttX in supervisor mode. This is obviously not usable in
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# flat mode, is questionable in protected mode, but is mandatory in kernel
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# mode.
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#
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# Kernel mode requires this as M-mode uses flat addressing and the kernel
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# memory must be mapped in order to share memory between the kernel and
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# different user tasks which reside in virtual memory.
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#
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# Note that S-mode requires a companion software (SBI)
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#
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config ARCH_USE_S_MODE
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bool "Run the NuttX kernel in S-mode"
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default n
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depends on ARCH_HAVE_S_MODE && BUILD_KERNEL && ARCH_USE_MMU
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---help---
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Most of the RISC-V implementations run in M-mode (flat addressing)
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and/or U-mode (in case of separate kernel-/userspaces). This provides
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an option to run the kernel in S-mode, if the target supports it.
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# MPU has certain architecture dependent configurations, which are presented
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# here. Default is that the full RISC-V PMP specification is supported.
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config PMP_HAS_LIMITED_FEATURES
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bool
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default n
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config ARCH_MPU_MIN_BLOCK_SIZE
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int "Minimum MPU (PMP) block size"
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default 4 if !PMP_HAS_LIMITED_FEATURES
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config ARCH_MPU_HAS_TOR
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bool "PMP supports TOR"
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default y if !PMP_HAS_LIMITED_FEATURES
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config ARCH_MPU_HAS_NO4
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bool "PMP supports NO4"
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default y if !PMP_HAS_LIMITED_FEATURES
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config ARCH_MPU_HAS_NAPOT
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bool "PMP supports NAPOT"
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default y if !PMP_HAS_LIMITED_FEATURES
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choice
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prompt "Toolchain Selection"
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default RISCV_TOOLCHAIN_GNU_RV64
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config RISCV_TOOLCHAIN_GNU_RV64
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bool "Generic GNU RV64 toolchain"
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select ARCH_TOOLCHAIN_GNU
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---help---
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This option should work for any modern GNU toolchain (GCC 5.2 or newer)
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configured for riscv64-unknown-elf.
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config RISCV_TOOLCHAIN_GNU_RV32
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bool "Generic GNU RV32 toolchain"
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select ARCH_TOOLCHAIN_GNU
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---help---
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This option should work for any modern GNU toolchain (GCC 5.2 or newer)
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configured for riscv32-unknown-elf.
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endchoice
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config RISCV_SEMIHOSTING_HOSTFS
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bool "Semihosting HostFS"
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depends on FS_HOSTFS
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---help---
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Mount HostFS through semihosting.
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This doesn't support some directory operations like readdir because
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of the limitations of semihosting mechanism.
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if RISCV_SEMIHOSTING_HOSTFS
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config RISCV_SEMIHOSTING_HOSTFS_CACHE_COHERENCE
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bool "Cache coherence in semihosting hostfs"
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depends on ARCH_DCACHE
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---help---
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Flush & Invalidte cache before & after bkpt instruction.
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endif
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if ARCH_CHIP_LITEX
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choice
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prompt "LITEX Core Selection"
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default LITEX_CORE_VEXRISCV
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config LITEX_CORE_VEXRISCV
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bool "vexriscv core"
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config LITEX_CORE_VEXRISCV_SMP
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bool "vexriscv_smp core"
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MMU
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select ARCH_RV_ISA_C
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select ARCH_MMU_TYPE_SV32
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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select ARCH_HAVE_S_MODE
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select ARCH_HAVE_ELF_EXECUTABLE
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endchoice
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endif
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source "arch/risc-v/src/opensbi/Kconfig"
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source "arch/risc-v/src/nuttsbi/Kconfig"
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if ARCH_CHIP_FE310
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source "arch/risc-v/src/fe310/Kconfig"
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endif
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if ARCH_CHIP_K210
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source "arch/risc-v/src/k210/Kconfig"
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endif
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if ARCH_CHIP_LITEX
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source "arch/risc-v/src/litex/Kconfig"
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endif
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if ARCH_CHIP_BL602
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source "arch/risc-v/src/bl602/Kconfig"
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endif
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if ARCH_CHIP_ESP32C3
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source "arch/risc-v/src/esp32c3/Kconfig"
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endif
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if ARCH_CHIP_ESP32C6
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source "arch/risc-v/src/esp32c6/Kconfig"
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endif
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if ARCH_CHIP_ESPRESSIF
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source "arch/risc-v/src/espressif/Kconfig"
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endif
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if ARCH_CHIP_C906
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source "arch/risc-v/src/c906/Kconfig"
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endif
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if ARCH_CHIP_MPFS
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source "arch/risc-v/src/mpfs/Kconfig"
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endif
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if ARCH_CHIP_RV32M1
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source "arch/risc-v/src/rv32m1/Kconfig"
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endif
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if ARCH_CHIP_QEMU_RV
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source "arch/risc-v/src/qemu-rv/Kconfig"
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endif
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if ARCH_CHIP_HPM6750
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source "arch/risc-v/src/hpm6750/Kconfig"
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endif
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if ARCH_CHIP_JH7110
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source "arch/risc-v/src/jh7110/Kconfig"
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endif
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endif
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