533 lines
13 KiB
Plaintext
533 lines
13 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_ARM
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comment "ARM Options"
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choice
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prompt "ARM chip selection"
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default ARCH_CHIP_STM32
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config ARCH_CHIP_A1X
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bool "Allwinner A1X"
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select ARCH_CORTEXA8
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select ARCH_HAVE_FPU
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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select ARCH_HAVE_LOWVECTORS
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select ARCH_HAVE_SDRAM
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select BOOT_RUNFROMSDRAM
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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Allwinner A1X family: A10, A10S (A12), A13 (ARM Cortex-A8)
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config ARCH_CHIP_C5471
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bool "TMS320 C5471"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_LOWVECTORS
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select ARCH_HAVE_OTHER_UART
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---help---
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TI TMS320 C5471, A180, or DA180 (ARM7TDMI)
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config ARCH_CHIP_CALYPSO
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bool "Calypso"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_HEAP2
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select ARCH_HAVE_LOWVECTORS
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select ARCH_HAVE_OTHER_UART
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select ARCH_HAVE_POWEROFF
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---help---
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TI Calypso-based cell phones (ARM7TDMI)
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config ARCH_CHIP_DM320
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bool "TMS320 DM320"
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select ARCH_ARM926EJS
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select ARCH_HAVE_LOWVECTORS
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---help---
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TI DMS320 DM320 (ARM926EJS)
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config ARCH_CHIP_EFM32
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bool "Energy Micro"
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select ARCH_HAVE_CMNVECTOR
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select ARMV7M_CMNVECTOR
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---help---
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Energy Micro EFM32 microcontrollers (ARM Cortex-M).
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config ARCH_CHIP_IMX
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bool "Freescale iMX"
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select ARCH_ARM920T
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select ARCH_HAVE_HEAP2
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select ARCH_HAVE_LOWVECTORS
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---help---
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Freescale iMX architectures (ARM920T)
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config ARCH_CHIP_KINETIS
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bool "Freescale Kinetis"
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select ARCH_CORTEXM4
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FPU
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select ARCH_HAVE_RAMFUNCS
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---help---
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Freescale Kinetis Architectures (ARM Cortex-M4)
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config ARCH_CHIP_KL
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bool "Freescale Kinetis L"
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select ARCH_CORTEXM0
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select ARCH_HAVE_CMNVECTOR
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---help---
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Freescale Kinetis L Architectures (ARM Cortex-M0+)
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config ARCH_CHIP_LM
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bool "TI/Luminary Stellaris"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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---help---
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TI/Luminary Stellaris LMS3 and LM4F architectures (ARM Cortex-M3/4)
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config ARCH_CHIP_TIVA
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bool "TI Tiva"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FPU
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---help---
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TI Tiva TM4C architectures (ARM Cortex-M4)
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config ARCH_CHIP_LPC11XX
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bool "NXP LPC11xx"
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select ARCH_CORTEXM0
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select ARCH_HAVE_CMNVECTOR
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---help---
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NXP LPC11xx architectures (ARM Cortex-M0)
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config ARCH_CHIP_LPC17XX
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bool "NXP LPC17xx"
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select ARCH_CORTEXM3
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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---help---
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NXP LPC17xx architectures (ARM Cortex-M3)
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config ARCH_CHIP_LPC214X
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bool "NXP LPC214x"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_LOWVECTORS
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---help---
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NXP LPC2145x architectures (ARM7TDMI)
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config ARCH_CHIP_LPC2378
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bool "NXP LPC2378"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_LOWVECTORS
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---help---
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NXP LPC2145x architectures (ARM7TDMI)
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config ARCH_CHIP_LPC31XX
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bool "NXP LPC31XX"
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select ARCH_ARM926EJS
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select ARCH_HAVE_LOWVECTORS
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---help---
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NPX LPC31XX architectures (ARM926EJS).
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config ARCH_CHIP_LPC43XX
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bool "NXP LPC43XX"
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select ARCH_CORTEXM4
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select ARCH_HAVE_CMNVECTOR
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select ARMV7M_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FPU
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---help---
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NPX LPC43XX architectures (ARM Cortex-M4).
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config ARCH_CHIP_NUC1XX
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bool "Nuvoton NUC100/120"
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select ARCH_CORTEXM0
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select ARCH_HAVE_CMNVECTOR
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---help---
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NPX LPC43XX architectures (ARM Cortex-M4).
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config ARCH_CHIP_SAMA5
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bool "Atmel SAMA5"
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select ARCH_CORTEXA5
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select ARCH_HAVE_FPU
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select ARCH_HAVE_LOWVECTORS
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_TICKLESS
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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Atmel SAMA5 (ARM Cortex-A5)
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config ARCH_CHIP_SAMD
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bool "Atmel SAMD"
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select ARCH_CORTEXM0
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select ARCH_HAVE_CMNVECTOR
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---help---
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Atmel SAMD (ARM Cortex-M0+)
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config ARCH_CHIP_SAML
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bool "Atmel SAML"
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select ARCH_CORTEXM0
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select ARCH_HAVE_CMNVECTOR
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---help---
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Atmel SAML (ARM Cortex-M0+)
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config ARCH_CHIP_SAM34
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bool "Atmel SAM3/SAM4"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARCH_HAVE_RAMFUNCS
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select ARMV7M_HAVE_STACKCHECK
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---help---
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Atmel SAM3 (ARM Cortex-M3) and SAM4 (ARM Cortex-M4) architectures
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config ARCH_CHIP_SAMV7
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bool "Atmel SAMV7"
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select ARCH_HAVE_CMNVECTOR
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select ARMV7M_CMNVECTOR
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select ARCH_CORTEXM7
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select ARCH_HAVE_MPU
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select ARCH_HAVE_RAMFUNCS
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select ARMV7M_HAVE_STACKCHECK
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---help---
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Atmel SAMV7 (ARM Cortex-M7) architectures
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config ARCH_CHIP_STM32
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bool "STMicro STM32 F1/F2/F3/F4"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_HEAPCHECK
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select ARMV7M_HAVE_STACKCHECK
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---help---
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STMicro STM32 architectures (ARM Cortex-M3/4).
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config ARCH_CHIP_STM32F7
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bool "STMicro STM32 F7"
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select ARCH_HAVE_CMNVECTOR
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select ARMV7M_CMNVECTOR
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select ARCH_CORTEXM7
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select ARCH_HAVE_MPU
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select ARCH_HAVE_RAMFUNCS
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select ARMV7M_HAVE_STACKCHECK
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---help---
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STMicro STM32 architectures (ARM Cortex-M7).
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config ARCH_CHIP_STR71X
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bool "STMicro STR71x"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_LOWVECTORS
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---help---
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STMicro STR71x architectures (ARM7TDMI).
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endchoice
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config ARCH_ARM7TDMI
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bool
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default n
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config ARCH_ARM926EJS
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bool
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default n
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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config ARCH_ARM920T
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bool
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default n
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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config ARCH_CORTEXM0
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bool
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default n
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_RESET
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config ARCH_CORTEXM3
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bool
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default n
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_RAMVECTORS
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select ARCH_HAVE_HIPRI_INTERRUPT
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select ARCH_HAVE_RESET
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config ARCH_CORTEXM4
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bool
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default n
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_RAMVECTORS
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select ARCH_HAVE_HIPRI_INTERRUPT
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select ARCH_HAVE_RESET
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config ARCH_CORTEXM7
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bool
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default n
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select ARCH_HAVE_FPU
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_RAMVECTORS
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select ARCH_HAVE_HIPRI_INTERRUPT
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config ARCH_CORTEXA5
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bool
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default n
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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select ARCH_HAVE_COHERENT_DCACHE if ELF
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config ARCH_CORTEXA8
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bool
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default n
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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select ARCH_HAVE_COHERENT_DCACHE if ELF
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config ARCH_FAMILY
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string
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default "arm" if ARCH_ARM7TDMI || ARCH_ARM926EJS || ARCH_ARM920T
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default "armv6-m" if ARCH_CORTEXM0
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default "armv7-a" if ARCH_CORTEXA5 || ARCH_CORTEXA8
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default "armv7-m" if ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
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config ARCH_CHIP
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string
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default "a1x" if ARCH_CHIP_A1X
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default "c5471" if ARCH_CHIP_C5471
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default "calypso" if ARCH_CHIP_CALYPSO
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default "dm320" if ARCH_CHIP_DM320
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default "efm32" if ARCH_CHIP_EFM32
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default "imx" if ARCH_CHIP_IMX
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default "kinetis" if ARCH_CHIP_KINETIS
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default "kl" if ARCH_CHIP_KL
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default "tiva" if ARCH_CHIP_LM || ARCH_CHIP_TIVA
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default "lpc11xx" if ARCH_CHIP_LPC11XX
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default "lpc17xx" if ARCH_CHIP_LPC17XX
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default "lpc214x" if ARCH_CHIP_LPC214X
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default "lpc2378" if ARCH_CHIP_LPC2378
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default "lpc31xx" if ARCH_CHIP_LPC31XX
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default "lpc43xx" if ARCH_CHIP_LPC43XX
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default "nuc1xx" if ARCH_CHIP_NUC1XX
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default "sama5" if ARCH_CHIP_SAMA5
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default "samdl" if ARCH_CHIP_SAMD || ARCH_CHIP_SAML
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default "sam34" if ARCH_CHIP_SAM34
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default "samv7" if ARCH_CHIP_SAMV7
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default "stm32" if ARCH_CHIP_STM32
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default "stm32f7" if ARCH_CHIP_STM32F7
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default "str71x" if ARCH_CHIP_STR71X
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config ARMV7M_USEBASEPRI
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bool "Use BASEPRI Register"
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default n
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depends on ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
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---help---
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Use the BASEPRI register to enable and disable interrupts. By
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default, the PRIMASK register is used for this purpose. This
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usually results in hardfaults when supervisor calls are made.
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Though, these hardfaults are properly handled by the RTOS, the
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hardfaults can confuse some debuggers. With the BASEPRI
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register, these hardfaults, will be avoided. For more details see
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http://www.nuttx.org/doku.php?id=wiki:nxinternal:svcall
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config ARCH_HAVE_CMNVECTOR
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bool
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config ARMV7M_CMNVECTOR
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bool "Use common ARMv7-M vectors"
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default n
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depends on ARCH_HAVE_CMNVECTOR
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---help---
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Some architectures use their own, built-in vector logic. Some use only
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the common vector logic. Some can use either their own built-in vector
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logic or the common vector logic. This applies only to ARMv7-M
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architectures.
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config ARMV7M_LAZYFPU
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bool "Lazy FPU storage"
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default n
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depends on ARCH_HAVE_CMNVECTOR
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---help---
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There are two forms of the common vector logic. There are pros and
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cons to each option:
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1) The standard common vector logic exploits features of the ARMv7-M
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architecture to save the all of floating registers on entry into
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each interrupt and then to restore the floating registers when
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the interrupt returns. The primary advantage to this approach is
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that floating point operations are available in interrupt
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handling logic. Since the volatile registers are preserved,
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operations on the floating point registers by interrupt handling
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logic has no ill effect. The downside is, of course, that more
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stack operations are required on each interrupt to save and store
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the floating point registers. Because of the some special
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features of the ARMv-M, this is not as much overhead as you might
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expect, but overhead nonetheless.
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2) The lazy FPU common vector logic does not save or restore
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floating point registers on entry and exit from the interrupt
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handler. Rather, the floating point registers are not restored
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until it is absolutely necessary to do so when a context switch
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occurs and the interrupt handler will be returning to a different
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floating point context. Since floating point registers are not
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protected, floating point operations must not be performed in
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interrupt handling logic. Better interrupt performance is be
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expected, however.
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By default, the "standard" common vector logic is build. This
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option selects the alternate lazy FPU common vector logic.
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config ARCH_HAVE_FPU
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bool
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default n
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config ARCH_HAVE_DPFPU
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bool
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default n
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config ARCH_FPU
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bool "FPU support"
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default y
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depends on ARCH_HAVE_FPU
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---help---
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Build in support for the ARM Cortex-M4 Floating Point Unit (FPU).
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Check your chip specifications first; not all Cortex-M4 chips
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support the FPU.
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config ARCH_DPFPU
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bool "Double precision FPU support"
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default y
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depends on ARCH_FPU && ARCH_HAVE_DPFPU
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---help---
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Enable toolchain support for double precision (64-bit) floating
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point if both the toolchain and the hardware support it.
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config ARMV7M_MPU
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bool "MPU support"
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default n
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depends on ARCH_HAVE_MPU
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select ARCH_USE_MPU
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---help---
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Build in support for the ARM Cortex-M3/4 Memory Protection Unit (MPU).
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Check your chip specifications first; not all Cortex-M3/4 chips
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support the MPU.
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config ARMV7M_MPU_NREGIONS
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int "Number of MPU regions"
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default 8
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depends on ARMV7M_MPU
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---help---
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This is the number of protection regions supported by the MPU.
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config ARCH_HAVE_LOWVECTORS
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bool
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config ARCH_LOWVECTORS
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bool "Vectors in low memory"
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default n
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depends on ARCH_HAVE_LOWVECTORS
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---help---
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Support ARM vectors in low memory.
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config ARCH_ROMPGTABLE
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bool "ROM page table"
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default n
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depends on ARCH_USE_MMU
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---help---
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Support a fixed memory mapping use a (read-only) page table in ROM/FLASH.
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config DEBUG_HARDFAULT
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bool "Verbose Hard-Fault Debug"
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default n
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depends on DEBUG && (ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7)
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---help---
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Enables verbose debug output when a hard fault is occurs. This verbose
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output is sometimes helpful when debugging difficult hard fault problems,
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but may be more than you typcially want to see.
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if ARCH_CORTEXM0
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source arch/arm/src/armv6-m/Kconfig
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endif
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if ARCH_CORTEXA5 || ARCH_CORTEXA8
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source arch/arm/src/armv7-a/Kconfig
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endif
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if ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
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source arch/arm/src/armv7-m/Kconfig
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endif
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if ARCH_ARM7TDMI || ARCH_ARM926EJS
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source arch/arm/src/arm/Kconfig
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endif
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if ARCH_CHIP_A1X
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source arch/arm/src/a1x/Kconfig
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endif
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if ARCH_CHIP_C5471
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source arch/arm/src/c5471/Kconfig
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endif
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if ARCH_CHIP_CALYPSO
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source arch/arm/src/calypso/Kconfig
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endif
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if ARCH_CHIP_DM320
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source arch/arm/src/dm320/Kconfig
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endif
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if ARCH_CHIP_EFM32
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source arch/arm/src/efm32/Kconfig
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endif
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if ARCH_CHIP_IMX
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source arch/arm/src/imx/Kconfig
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endif
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if ARCH_CHIP_KINETIS
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source arch/arm/src/kinetis/Kconfig
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endif
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if ARCH_CHIP_KL
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source arch/arm/src/kl/Kconfig
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endif
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if ARCH_CHIP_LM || ARCH_CHIP_TIVA
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source arch/arm/src/tiva/Kconfig
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endif
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if ARCH_CHIP_LPC11XX
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source arch/arm/src/lpc11xx/Kconfig
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endif
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if ARCH_CHIP_LPC17XX
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source arch/arm/src/lpc17xx/Kconfig
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endif
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if ARCH_CHIP_LPC214X
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source arch/arm/src/lpc214x/Kconfig
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endif
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if ARCH_CHIP_LPC2378
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source arch/arm/src/lpc2378/Kconfig
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endif
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if ARCH_CHIP_LPC31XX
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source arch/arm/src/lpc31xx/Kconfig
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endif
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if ARCH_CHIP_LPC43XX
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source arch/arm/src/lpc43xx/Kconfig
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endif
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if ARCH_CHIP_NUC1XX
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source arch/arm/src/nuc1xx/Kconfig
|
|
endif
|
|
if ARCH_CHIP_SAMA5
|
|
source arch/arm/src/sama5/Kconfig
|
|
endif
|
|
if ARCH_CHIP_SAMD || ARCH_CHIP_SAML
|
|
source arch/arm/src/samdl/Kconfig
|
|
endif
|
|
if ARCH_CHIP_SAM34
|
|
source arch/arm/src/sam34/Kconfig
|
|
endif
|
|
if ARCH_CHIP_SAMV7
|
|
source arch/arm/src/samv7/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STM32
|
|
source arch/arm/src/stm32/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STM32F7
|
|
source arch/arm/src/stm32f7/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STR71X
|
|
source arch/arm/src/str71x/Kconfig
|
|
endif
|
|
|
|
endif
|