231b8518b7
Ken Pettit has submitted the ICLA and we can migrate the licenses to Apache. Sebastien Lorquet has submitted the ICLA and we can migrate the licenses to Apache. Gregory Nutt has submitted the SGA and we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
140 lines
4.5 KiB
C
140 lines
4.5 KiB
C
/****************************************************************************
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* boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include "arm_arch.h"
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#include "mikroe-stm32f4.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_board_clockconfig
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*
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* Description:
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* The Mikroe-STM32F4 board does not have an external crystal, so it must
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* rely on the internal 16Mhz RC oscillator. The default clock
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* configuration in the OS for the STM32 architecture assumes an external
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* crystal, so we must provide a board specific clock configuration
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* routine.
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*
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****************************************************************************/
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#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
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void stm32_board_clockconfig(void)
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{
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uint32_t regval;
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/* Configure chip clocking to use the internal 16Mhz RC oscillator.
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*
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* NOTE: We will assume the HSIRDY (High Speed Internal RC Ready) bit is
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* set, otherwise we wouldn't be here executing code.
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*/
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regval = getreg32(STM32_RCC_APB1ENR);
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regval |= RCC_APB1ENR_PWREN;
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putreg32(regval, STM32_RCC_APB1ENR);
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regval = getreg32(STM32_PWR_CR);
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regval |= PWR_CR_VOS;
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putreg32(regval, STM32_PWR_CR);
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/* Set the HCLK source/divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_HPRE_MASK;
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regval |= STM32_RCC_CFGR_HPRE;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PCLK2 divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_PPRE2_MASK;
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regval |= STM32_RCC_CFGR_PPRE2;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PCLK1 divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_PPRE1_MASK;
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regval |= STM32_RCC_CFGR_PPRE1;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PLL dividers and multipliers to configure the main PLL */
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regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP |
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RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ);
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putreg32(regval, STM32_RCC_PLLCFG);
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/* Enable the main PLL */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_PLLON;
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the PLL is ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0)
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;
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/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait
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* states
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*/
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#ifdef CONFIG_STM32_FLASH_PREFETCH
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regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN |
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FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
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#else
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regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
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#endif
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putreg32(regval, STM32_FLASH_ACR);
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/* Select the main PLL as system clock source */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_SW_MASK;
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regval |= RCC_CFGR_SW_PLL;
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putreg32(regval, STM32_RCC_CFGR);
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/* Wait until the PLL source is used as the system clock source */
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while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
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;
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}
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#endif
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