Ville Juven 370152f3ba RISC-V: Move mhartid to own assembly macro+function ...

Hartid and cpuindex are not the same thing. Hartid is needed regardless
of SMP, for external interrupt handling etc.

SMP needs cpuindex which might not be index == hartid, so both are
needed. IMO it is clearer to provide separate API for both.

Currently the implementation of up_cpu_index is done a bit lazily,
because it assumes hartid == cpu index, but this is not 100% accurate,
so it is still missing some logic.

2022-04-13 12:00:40 +02:00

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supervisor

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addrenv.h

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riscv_addrenv_kstack.c

RISC-V: Include support for kernel stack

2022-03-24 00:15:28 +08:00

riscv_allocateheap.c

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riscv_assert.c

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riscv_backtrace.c

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riscv_blocktask.c

arch/risc-v: Remove unneeded group_addrenv call which handled by riscv_doirq

2022-03-31 19:33:08 +08:00

riscv_checkstack.c

arch/risc-v: Remove the unnecessary inclusion of board header files

2022-04-07 11:25:12 +03:00

riscv_copystate.c

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riscv_cpuidlestack.c

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riscv_cpuindex.c

RISC-V: Move mhartid to own assembly macro+function

2022-04-13 12:00:40 +02:00

riscv_cpupause.c

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riscv_cpustart.c

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riscv_createstack.c

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riscv_doirq.c

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riscv_exception_common.S

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riscv_exception.c

arch/risc-v: Apply misaligned access handler for k210/bl602

2022-04-13 01:10:49 +08:00

riscv_exit.c

arch/risc-v: Remove unneeded group_addrenv call which handled by riscv_doirq

2022-03-31 19:33:08 +08:00

riscv_fpu.S

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riscv_getnewintctx.c

RISC-V: Implement option to run NuttX in supervisor mode (S-mode)

2022-04-01 16:19:42 -03:00

riscv_idle.c

risc-v: Support cpu activity led in up_idle

2022-02-10 13:09:32 +08:00

riscv_initialize.c

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riscv_initialstate.c

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riscv_internal.h

arch/risc-v: Attach exception handler in common place

2022-04-10 00:52:04 +08:00

riscv_interruptcontext.c

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riscv_macros.S

RISC-V: Move mhartid to own assembly macro+function

2022-04-13 12:00:40 +02:00

riscv_mdelay.c

arch: risc-V: Author Gregory Nutt: update licenses to Apache

2021-03-31 08:48:51 -07:00

riscv_mhartid.S

RISC-V: Move mhartid to own assembly macro+function

2022-04-13 12:00:40 +02:00

riscv_misaligned.c

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riscv_mmu.c

arch/risc-v: include csr.h indirectly through nuttx/irq.h

2022-03-31 19:34:52 +08:00

riscv_mmu.h

MPFS: Add board_memorymap.h

2022-03-18 09:35:00 -03:00

riscv_modifyreg32.c

arch: Merge up_arch.h into up_internal.h

2022-03-14 09:32:17 +02:00

riscv_mtimer.c

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riscv_mtimer.h

arch/riscv: Add mtimer driver

2022-04-11 10:59:18 +03:00

riscv_percpu.c

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riscv_percpu.h

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riscv_pmp.c

arch/risc-v: include csr.h indirectly through nuttx/irq.h

2022-03-31 19:34:52 +08:00

riscv_pthread_start.c

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riscv_puts.c

arch/riscv: Rename riscv_puts to up_puts

2021-09-18 07:33:44 -03:00

riscv_releasepending.c

arch/risc-v: Remove unneeded group_addrenv call which handled by riscv_doirq

2022-03-31 19:33:08 +08:00

riscv_releasestack.c

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riscv_reprioritizertr.c

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riscv_schedulesigaction.c

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riscv_sigdeliver.c

arch/risc-v: Improve performance of context switch

2022-03-26 07:19:09 +09:00

riscv_signal_dispatch.c

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riscv_signal_handler.S

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riscv_stackframe.c

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riscv_swint.c

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riscv_task_start.c

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riscv_tcbinfo.c

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riscv_testset.S

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riscv_tls.c

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riscv_udelay.c

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riscv_unblocktask.c

arch/risc-v: Remove unneeded group_addrenv call which handled by riscv_doirq

2022-03-31 19:33:08 +08:00

riscv_usestack.c

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riscv_vectors.S

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riscv_vfork.c

arch/risc-v: Merge rv32im and rv64gc into common

2022-01-11 23:24:33 +08:00

riscv_vfork.h

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Toolchain.defs

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