d42fc094fa
arm: stm32: codestyle fixes
* arm: stm32f0l0g0: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32f7: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32h7: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32l4: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
140 lines
4.9 KiB
C
140 lines
4.9 KiB
C
/****************************************************************************
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* boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include "chip.h"
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#include "up_arch.h"
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#include "stm32.h"
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#include "stm3210e-eval.h"
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#ifdef CONFIG_STM32_FSMC
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#if STM32_NGPIO_PORTS < 6
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# error "Required GPIO ports not enabled"
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* Pin Usage (per schematic)
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*
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* FLASH SRAM NAND LCD
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* D[0..15] [0..15] [0..15] [0..7] [0..15]
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* A[0..23] [0..22] [0..18] [16,17] [0]
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* FSMC_NBL0 PE0 OUT ~BLE --- --- ---
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* FSMC_NBL1 PE1 OUT ~BHE --- --- ---
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* FSMC_NE2 PG9 OUT --- ~E --- ---
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* FSMC_NE3 PG10 OUT ~CE --- --- ---
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* FSMC_NE4 PG12 OUT --- --- --- ~CS
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* FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL
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* FSMC_NOE PD4 OUT ~OE ~G ~R ~RD
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* FSMC_NWAIT PD6 IN --- R~B --- ---
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* FSMC_INT2 PG6* IN --- --- R~B ---
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*
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* *JP7 will switch to PD6
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*/
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/* GPIO configurations unique to NOR Flash */
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static const uint16_t g_norconfig[] =
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{
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/* A19... A22 */
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GPIO_NPS_A19, GPIO_NPS_A20, GPIO_NPS_A21, GPIO_NPS_A22,
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/* NE2 */
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GPIO_NPS_NE2
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};
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#define NNOR_CONFIG (sizeof(g_norconfig)/sizeof(uint16_t))
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_selectnor
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*
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* Description:
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* Initialize to access NOR flash
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*
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****************************************************************************/
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void stm32_selectnor(void)
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{
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/* Configure new GPIO state */
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stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG);
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stm32_extmemgpios(g_norconfig, NNOR_CONFIG);
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/* Enable AHB clocking to the FSMC */
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stm32_fsmc_enable();
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/* Bank1 NOR/SRAM control register configuration */
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putreg32(FSMC_BCR_NOR|FSMC_BCR_FACCEN|FSMC_BCR_MWID16|FSMC_BCR_WREN, STM32_FSMC_BCR2);
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/* Bank1 NOR/SRAM timing register configuration */
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putreg32(FSMC_BTR_ADDSET(3)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(6)|FSMC_BTR_BUSTURN(1)|
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FSMC_BTR_CLKDIV(1)|FSMC_BTR_DATLAT(2)|FSMC_BTR_ACCMODB, STM32_FSMC_BTR2);
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putreg32(0x0fffffff, STM32_FSMC_BWTR2);
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/* Enable the bank */
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putreg32(FSMC_BCR_MBKEN|FSMC_BCR_NOR|FSMC_BCR_FACCEN|FSMC_BCR_MWID16|FSMC_BCR_WREN, STM32_FSMC_BCR2);
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}
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#endif /* CONFIG_STM32_FSMC */
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