Huang Qi 384610b253 riscv: Add indirect CSRs for CLIC
Add indirect CSR registers for RISC-V Core-Local Interrupt Controller (CLIC) Privileged Architecture Extensions.

Refer to: https://github.com/riscv/riscv-fast-interrupt

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-06-21 03:02:59 +08:00
..
2024-06-18 00:17:07 +08:00
2024-05-13 22:24:36 +02:00
2024-06-21 03:02:59 +08:00