384610b253
Add indirect CSR registers for RISC-V Core-Local Interrupt Controller (CLIC) Privileged Architecture Extensions. Refer to: https://github.com/riscv/riscv-fast-interrupt Signed-off-by: Huang Qi <huangqi3@xiaomi.com> |
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arm | ||
arm64 | ||
avr | ||
ceva | ||
dummy | ||
hc | ||
mips | ||
misoc | ||
or1k | ||
renesas | ||
risc-v | ||
sim | ||
sparc | ||
tricore | ||
x86 | ||
x86_64 | ||
xtensa | ||
z16 | ||
z80 | ||
CMakeLists.txt | ||
Kconfig |