Huang Qi 384610b253 riscv: Add indirect CSRs for CLIC ...

Add indirect CSR registers for RISC-V Core-Local Interrupt Controller (CLIC) Privileged Architecture Extensions.

Refer to: https://github.com/riscv/riscv-fast-interrupt

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>

2024-06-21 03:02:59 +08:00

..

include

riscv: Add indirect CSRs for CLIC

2024-06-21 03:02:59 +08:00

src

arch/risc-v: Improve the SBI function handle

2024-06-19 20:55:10 +08:00

CMakeLists.txt

cmake:init RISC-V cmake qemu-rv build

2023-10-26 21:01:46 +08:00

Kconfig

arch/risc-v: Add support for SOPHGO SG2000 SoC (T-Head C906)

2024-06-17 09:41:29 +08:00