359 lines
12 KiB
ArmAsm
359 lines
12 KiB
ArmAsm
/************************************************************************************************
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* arch/arm/src/armv7-m/sam_vectors.S
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*
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* Copyright (C) 2009-2010, 2013-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************************/
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/************************************************************************************************
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* Included Files
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************************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include "exc_return.h"
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#include "chip.h"
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/************************************************************************************************
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* Pre-processor Definitions
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************************************************************************************************/
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/* Configuration ********************************************************************************/
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#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
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/* In kernel mode without an interrupt stack, this interrupt handler will set the MSP to the
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* stack pointer of the interrupted thread. If the interrupted thread was a privileged
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* thread, that will be the MSP otherwise it will be the PSP. If the PSP is used, then the
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* value of the MSP will be invalid when the interrupt handler returns because it will be a
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* pointer to an old position in the unprivileged stack. Then when the high priority
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* interrupt occurs and uses this stale MSP, there will most likely be a system failure.
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*
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* If the interrupt stack is selected, on the other hand, then the interrupt handler will
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* always set the the MSP to the interrupt stack. So when the high priority interrupt occurs,
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* it will either use the MSP of the last privileged thread to run or, in the case of the
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* nested interrupt, the interrupt stack if no privileged task has run.
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*/
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# if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4
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# error Interrupt stack must be used with high priority interrupts in kernel mode
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# endif
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/* Use the the BASEPRI to control interrupts is required if nested, high
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* priority interrupts are supported.
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*/
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# ifndef CONFIG_ARMV7M_USEBASEPRI
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# error CONFIG_ARMV7M_USEBASEPRI must be used with CONFIG_ARCH_HIPRI_INTERRUPT
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# endif
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#endif
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/************************************************************************************************
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* Global Symbols
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************************************************************************************************/
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.globl exception_common
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.syntax unified
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.thumb
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.file "up_lazyexception.S"
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/************************************************************************************************
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* .text
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************************************************************************************************/
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/* Common IRQ handling logic. On entry here, the return stack is on either
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* the PSP or the MSP and looks like the following:
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*
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* REG_XPSR
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* REG_R15
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* REG_R14
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* REG_R12
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* REG_R3
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* REG_R2
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* REG_R1
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* MSP->REG_R0
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*
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* And
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* IPSR contains the IRQ number
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* R14 Contains the EXC_RETURN value
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* We are in handler mode and the current SP is the MSP
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*/
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.text
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.type exception_common, function
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exception_common:
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/* Get the IRQ number from the IPSR */
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mrs r0, ipsr /* R0=exception number */
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/* Complete the context save */
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#ifdef CONFIG_BUILD_PROTECTED
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/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
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* (handler mode) if the stack is on the MSP. It can only be on the PSP if
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* EXC_RETURN is 0xfffffffd (unprivileged thread)
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*/
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tst r14, #EXC_RETURN_PROCESS_STACK /* nonzero if context on process stack */
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beq 1f /* Branch if context already on the MSP */
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mrs r1, psp /* R1=The process stack pointer (PSP) */
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mov sp, r1 /* Set the MSP to the PSP */
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1:
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#endif
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/* r1 holds the value of the stack pointer AFTER the exception handling logic
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* pushed the various registers onto the stack. Get r2 = the value of the
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* stack pointer BEFORE the interrupt modified it.
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*/
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mov r2, sp /* R2=Copy of the main/process stack pointer */
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add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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mrs r3, basepri /* R3=Current BASEPRI setting */
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#else
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mrs r3, primask /* R3=Current PRIMASK setting */
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#endif
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#ifdef CONFIG_ARCH_FPU
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/* Skip over the block of memory reserved for floating pointer register save.
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* Lazy FPU register saving is used. FPU registers will be saved in this
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* block only if a context switch occurs (this means, of course, that the FPU
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* cannot be used in interrupt processing).
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*/
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sub sp, #(4*SW_FPU_REGS)
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#endif
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/* Save the remaining registers on the stack after the registers pushed
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* by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
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* r14=register values.
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*/
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#ifdef CONFIG_BUILD_PROTECTED
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stmdb sp!, {r2-r11,r14} /* Save the remaining registers plus the SP value */
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#else
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stmdb sp!, {r2-r11} /* Save the remaining registers plus the SP value */
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#endif
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#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
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/* Disable interrupts, select the stack to use for interrupt handling
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* and call up_doirq to handle the interrupt
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*/
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cpsid i /* Disable further interrupts */
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#else
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/* Set the BASEPRI register so that further normal interrupts will be
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* masked. Nested, high priority may still occur, however.
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*/
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mov r2, #NVIC_SYSH_DISABLE_PRIORITY
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msr basepri, r2 /* Set the BASEPRI */
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#endif
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/* There are two arguments to up_doirq:
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*
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* R0 = The IRQ number
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* R1 = The top of the stack points to the saved state
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*/
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mov r1, sp
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will set the MSP to use
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* a special special interrupt stack pointer. The way that this is done
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* here prohibits nested interrupts without some additional logic!
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*/
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ldr sp, =g_intstackbase
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str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */
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bl up_doirq /* R0=IRQ, R1=register save (msp) */
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ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */
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#else
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/* Otherwise, we will re-use the interrupted thread's stack. That may
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* mean using either MSP or PSP stack for interrupt level processing (in
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* kernel mode).
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*/
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bl up_doirq /* R0=IRQ, R1=register save (msp) */
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mov r1, sp /* Recover R1=main stack pointer */
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#endif
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/* On return from up_doirq, R0 will hold a pointer to register context
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* array to use for the interrupt return. If that return value is the same
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* as current stack pointer, then things are relatively easy.
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*/
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cmp r0, r1 /* Context switch? */
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beq 2f /* Branch if no context switch */
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/* We are returning with a pending context switch.
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*
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* If the FPU is enabled, then we will need to restore FPU registers.
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* This is not done in normal interrupt save/restore because the cost
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* is prohibitive. This is only done when switching contexts. A
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* consequence of this is that floating point operations may not be
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* performed in interrupt handling logic.
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*
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* Here:
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* r0 = Address of the register save area
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* NOTE: It is a requirement that up_restorefpu() preserve the value of
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* r0!
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*/
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#ifdef CONFIG_ARCH_FPU
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bl up_restorefpu /* Restore the FPU registers */
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#endif
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/* We are returning with a pending context switch. This case is different
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* because in this case, the register save structure does not lie in the
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* stack but, rather, within a TCB structure. We'll have to copy some
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* values to the stack.
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*/
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add r1, r0, #SW_XCPT_SIZE /* R1=Address of HW save area in reg array */
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ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */
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ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */
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stmdb r1!, {r4-r11} /* Store eight registers in HW save area */
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#ifdef CONFIG_BUILD_PROTECTED
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ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */
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#else
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ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */
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#endif
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b 3f /* Re-join common logic */
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/* We are returning with no context switch. We simply need to "unwind"
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* the same stack frame that we created
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*
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* Here:
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* r1 = Address of the return stack (same as r0)
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*/
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2:
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#ifdef CONFIG_BUILD_PROTECTED
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ldmia r1!, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */
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#else
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ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */
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#endif
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#ifdef CONFIG_ARCH_FPU
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/* Skip over the block of memory reserved for floating pointer register
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* save. Then R1 is the address of the HW save area
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*/
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add r1, #(4*SW_FPU_REGS)
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#endif
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/* Set up to return from the exception
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*
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* Here:
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* r1 = Address on the target thread's stack position at the start of
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* the registers saved by hardware
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* r3 = primask or basepri
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* r4-r11 = restored register values
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*/
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3:
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#ifdef CONFIG_BUILD_PROTECTED
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/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
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* (handler mode) if the stack is on the MSP. It can only be on the PSP if
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* EXC_RETURN is 0xfffffffd (unprivileged thread)
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*/
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mrs r2, control /* R2=Contents of the control register */
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tst r14, #EXC_RETURN_PROCESS_STACK /* nonzero if context on process stack */
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beq 4f /* Branch if privileged */
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orr r2, r2, #1 /* Unprivileged mode */
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msr psp, r1 /* R1=The process stack pointer */
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b 5f
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4:
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bic r2, r2, #1 /* Privileged mode */
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msr msp, r1 /* R1=The main stack pointer */
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5:
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msr control, r2 /* Save the updated control register */
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#else
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msr msp, r1 /* Recover the return MSP value */
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/* Preload r14 with the special return value first (so that the return
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* actually occurs with interrupts still disabled).
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*/
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ldr r14, =EXC_RETURN_PRIVTHR /* Load the special value */
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#endif
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/* Restore the interrupt state */
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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msr basepri, r3 /* Restore interrupts priority masking */
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#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
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cpsie i /* Re-enable interrupts */
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#endif
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#else
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msr primask, r3 /* Restore interrupts */
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#endif
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/* Always return with R14 containing the special value that will: (1)
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* return to thread mode, and (2) continue to use the MSP
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*/
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bx r14 /* And return */
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.size exception_common, .-exception_common
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/************************************************************************************************
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* Name: g_intstackalloc/g_intstackbase
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*
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* Description:
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* Shouldn't happen
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*
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************************************************************************************************/
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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.bss
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.global g_intstackalloc
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.global g_intstackbase
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.align 4
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g_intstackalloc:
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.skip (CONFIG_ARCH_INTERRUPTSTACK & ~3)
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g_intstackbase:
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.size g_intstackalloc, .-g_intstackalloc
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#endif
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.end
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