Eero Nurkkala f5cdfa73dc risc-v/mpfs: clear L2 before use ... SiFive document: "ECC Error Handling Guide" states: "Any SRAM block or cache memory containing ECC functionality needs to be initialized prior to use. ECC will correct defective bits based on memory contents, so if memory is not first initialized to a known state, then ECC will not operate as expected. It is recommended to use a DMA, if available, to write the entire SRAM or cache to zeros prior to enabling ECC reporting. If no DMA is present, use store instructions issued from the processor." Clean the cache at this early stage so no ECC errors will be flooding later. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>		2023-09-01 19:28:54 +08:00
..
hss-nuttx.yml
kernel-space.ld	nuttx/boards:init_array.* needs to be executed in order	2023-08-29 22:54:37 +08:00
ld-envm-opensbi.script	risc-v/mpfs: clear L2 before use	2023-09-01 19:28:54 +08:00
ld-envm.script	risc-v/mpfs: clear L2 before use	2023-09-01 19:28:54 +08:00
ld-ihc-ch2.script	nuttx/boards:init_array.* needs to be executed in order	2023-08-29 22:54:37 +08:00
ld-ihc.script	nuttx/boards:init_array.* needs to be executed in order	2023-08-29 22:54:37 +08:00
ld-kernel.script	nuttx/boards:init_array.* needs to be executed in order	2023-08-29 22:54:37 +08:00
ld.script	nuttx/boards:init_array.* needs to be executed in order	2023-08-29 22:54:37 +08:00
Make.defs	arch/riscv: Move -mcmodel=medany from Make.defs to Toolchain.defs	2023-08-25 21:22:47 +03:00
memory.ld
user-space.ld	nuttx/boards:init_array.* needs to be executed in order	2023-08-29 22:54:37 +08:00