efa97ac0f5
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@157 42af7a65-404d-4744-a932-0658087f49c3
325 lines
9.0 KiB
ArmAsm
325 lines
9.0 KiB
ArmAsm
/********************************************************************
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* up_head.S
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*
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* Copyright (C) 2007 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name Gregory Nutt nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************/
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/********************************************************************
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* Included Files
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********************************************************************/
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#include <nuttx/config.h>
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#include "up_internal.h"
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#include "dm320.h"
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/**************************************************************************
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* Conditional Compilation
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**************************************************************************/
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#undef ALIGNMENT_TRAP
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#undef CPU_DCACHE_WRITETHROUGH
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#undef CPU_CACHE_ROUND_ROBIN
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#undef CPU_DCACHE_DISABLE
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#undef CPU_ICACHE_DISABLE
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/********************************************************************
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* Definitions
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********************************************************************/
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/* The physical address of the beginning of SDRAM is provided by
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* CONFIG_DRAM_BASE. The size of installed SDRAM is provided by
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* CONFIG_DRAM_SIZE. The virtual address of SDRAM is provided by
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* DM320_SDRAM_VADDR.
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*/
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#define NSDRAM_SECTIONS (CONFIG_DRAM_SIZE >> 20)
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/********************************************************************
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* Assembly Macros
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********************************************************************/
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/* Since the page table is closely related to the NuttX base
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* address, we can convert the page table base address to the
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* base address of the section containing both.
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*/
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.macro mksection, section, pgtable
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bic \section, \pgtable, #0x000ff000
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.endm
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/* This macro will modify r0, r1, r2 and r14 */
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#ifdef CONFIG_DEBUG
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.macro showprogress, code
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mov r0, #\code
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bl up_lowputc
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.endm
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#else
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.macro showprogress, code
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.endm
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#endif
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/********************************************************************
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* Name: __start
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********************************************************************/
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/* We assume the bootloader has already initialized most of the h/w for
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* us and that only leaves us having to do some os specific things
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* below.
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*/
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.text
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.global __start
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.type __start, #function
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__start:
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/* Make sure that we are in SVC mode with all IRQs disabled */
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mov r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT)
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msr cpsr_c, r0
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/* Clear the 16K level 1 page table */
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ldr r4, .LCppgtable /* r4=phys. page table */
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mov r0, r4
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mov r1, #0
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add r2, r0, #PGTABLE_SIZE
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.Lpgtableclear:
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str r1, [r0], #4
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str r1, [r0], #4
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str r1, [r0], #4
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str r1, [r0], #4
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teq r0, r2
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bne .Lpgtableclear
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/* Create identity mapping for first MB section to support
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* this startup logic executing out of the physical address
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* space. This identity mapping will be removed by .Lvstart
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* (see below).
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*/
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mksection r0, r4 /* r0=phys. base section */
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ldr r1, .LCmmuflags /* FLGS=MMU_MEMFLAGS */
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add r3, r1, r0 /* r3=flags + base */
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str r3, [r4, r0, lsr #18] /* identity mapping */
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/* Create a "normal" single section mapping for the first
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* MB of memory. Now, we have the first 1MB mapping to
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* both phyical and virtual addresses. The reset of the
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* SDRAM mapping will be completed in .Lvstart once we have
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* moved the physical mapping out of the way.
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*/
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ldr r2, .LCvpgtable /* r2=virt. page table */
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mksection r0, r2 /* r0=virt. base section */
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str r3, [r4, r0, lsr #18] /* identity mapping */
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/* The following logic will set up the ARM926 for normal operation */
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mov r0, #0
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mcr p15, 0, r0, c7, c7 /* Invalidate I,D caches */
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mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
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mcr p15, 0, r0, c8, c7 /* Invalidate I,D TLBs */
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mcr p15, 0, r4, c2, c0 /* Load page table pointer */
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#ifdef CPU_DCACHE_WRITETHROUGH
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mov r0, #4 /* Disable write-back on caches explicitly */
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mcr p15, 7, r0, c15, c0, 0
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#endif
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/* Enable the MMU and caches
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* lr = Resume at .Lvstart with the MMU enabled
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*/
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ldr lr, .LCvstart /* Abs. virtual address */
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mov r0, #0x1f /* Domains 0, 1 = client */
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mcr p15, 0, r0, c3, c0 /* Load domain access register */
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mrc p15, 0, r0, c1, c0 /* Get control register */
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/* Clear bits (see start.h) */
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bic r0, r0, #(CR_R|CR_F|CR_Z)
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bic r0, r0, #(CR_A|CR_C|CR_W)
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bic r0, r0, #(CR_I)
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/* Set bits (see start.h) */
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orr r0, r0, #(CR_M|CR_P|CR_D)
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orr r0, r0, #(CR_S|CR_V)
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#ifdef CPU_CACHE_ROUND_ROBIN
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orr r0, r0, #(CR_RR)
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#endif
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#ifndef CPU_DCACHE_DISABLE
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orr r0, r0, #(CR_C)
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#endif
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#ifndef CPU_ICACHE_DISABLE
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orr r0, r0, #(CR_I)
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#endif
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#ifdef ALIGNMENT_TRAP
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orr r0, r0, #(CR_A)
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#endif
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mcr p15, 0, r0, c1, c0, 0 /* write control reg */
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/* Get TMP=2 Processor ID register */
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mrc p15, 0, r1, c0, c0, 0 /* read id reg */
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mov r1, r1
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mov r1, r1
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mov pc, lr
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/**************************************************************************
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* PC_Relative Data
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**************************************************************************/
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/* These addresses are all virtual address */
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.type .LCvstart, %object
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.LCvstart:
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.long .Lvstart
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.type .LCmmuflags, %object
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.LCmmuflags:
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.long MMU_MEMFLAGS
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.type .LCppagetable, %object
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.LCppgtable:
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.long DM320_SDRAM_PADDR
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.type .LCvpagetable, %object
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.LCvpgtable:
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.long DM320_SDRAM_VADDR
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.size _start, .-_start
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/**************************************************************************
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* Name: .Lvstart
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**************************************************************************/
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/* The following is executed after the MMU has been enabled. This uses
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* absolute addresses; this is not position independent.
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*/
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.align 5
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.local .Lvstart
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.type .Lvstart, %function
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.Lvstart:
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/* Remove the temporary null mapping */
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ldr r4, .LCvpgtable /* r4=virtual page table */
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ldr r1, .LCppgtable /* r1=phys. page table */
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mksection r3, r1 /* r2=phys. base addr */
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mov r0, #0 /* flags + base = 0 */
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str r0, [r4, r3, lsr #18] /* Undo identity mapping */
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/* Now setup the pagetables for our normal SDRAM mappings
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* mapped region. We round NUTTX_START_VADDR down to the
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* nearest megabyte boundary.
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*/
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ldr r1, .LCmmuflags /* FLGS=MMU_MEMFLAGS */
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add r3, r3, r1 /* r3=flags + base */
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add r0, r4, #(NUTTX_START_VADDR & 0xff000000) >> 18
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bic r2, r3, #0x00f00000
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str r2, [r0]
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add r0, r0, #(NUTTX_START_VADDR & 0x00f00000) >> 18
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str r3, [r0], #4
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/* Now map the remaining NSDRAM_SECTIONS-1 SDRAM sections */
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.rept NSDRAM_SECTIONS-1
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add r3, r3, #SECTION_SIZE
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str r3, [r0], #4
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.endr
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/* Zero BSS and set up the stack pointer */
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adr r0, .Linitparms
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ldmia r0, {r0, r1, sp}
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/* Clear the frame pointer and .bss */
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mov fp, #0
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.Lbssinit:
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cmp r0, r1 /* Clear up to _bss_end_ */
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strcc fp, [r0],#4
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bcc .Lbssinit
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/* Perform early C-level initialization */
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bl up_boot
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/* Set up the LEDs */
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#ifdef CONFIG_ARCH_LEDS
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bl up_ledinit
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#endif
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/* Perform early serial initialization */
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#ifdef CONFIG_DEV_CONSOLE
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bl up_earlyserialinit
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#endif
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/* Finally branch to the OS entry point */
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mov lr, #0
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b os_start
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/* Variables:
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* _sbss is the start of the BSS region (see ld.script)
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* _ebss is the end of the BSS regsion (see ld.script)
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* The idle task stack starts at the end of BSS and is
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* of size CONFIG_PROC_STACK_SIZE. The heap continues
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* from there until the end of memory. See g_heapbase
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* below.
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*/
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.Linitparms:
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.long _sbss
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.long _ebss
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.long _ebss+CONFIG_PROC_STACK_SIZE-4
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.size .Lvstart, .-.Lvstart
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/* This global variable is unsigned long g_heapbase and is
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* exported from here only because of its coupling to .Linitparms
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* above.
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*/
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.data
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.align 4
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.globl g_heapbase
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.type g_heapbase, object
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g_heapbase:
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.long _ebss+CONFIG_PROC_STACK_SIZE
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.size g_heapbase, .-g_heapbase
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.end
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