nuttx/libs/libc/machine/risc-v
Ville Juven 9288ed85e7 RISC-V: Add/fix implementation for arch_elf.c
The jump instruction relocation had an assert that tests for jumps with
an offset of 0. This makes it so that a while(1); statement causes an
assert because the jump instruction points to the same address, which
is perfectly legal.

Addend was not handled correctly in several reloc types.

Add ADD32/64 + SUB32/64 relocations, for some reason the compiler
I use likes to add them.
2022-03-23 17:56:54 +08:00
..
common RISC-V: Add/fix implementation for arch_elf.c 2022-03-23 17:56:54 +08:00
rv32 Kconfig: improve uniformity 2021-12-14 07:32:48 -06:00
rv64 libc:machine:risc-v:unifying elf relocation code. 2021-02-19 11:09:18 -08:00
Kconfig arch/risc-v: Refine Toolchain.defs 2021-12-28 00:30:10 -06:00
Make.defs arch/risc-v: Refine Toolchain.defs 2021-12-28 00:30:10 -06:00