451 lines
15 KiB
C
451 lines
15 KiB
C
/****************************************************************************
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* arch/risc-v/include/gap8/irq.h
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* GAP8 event system
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: hhuysqt <1020988872@qq.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* GAP8 features a FC controller and a 8-core cluster. IRQ from peripherals
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* have unique ID, which are dispatched to the FC or cluster by the SOC
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* event unit, and then by the FC event unit or cluster event unit, and
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* finally to FC or cluster. Peripherals share the same IRQ entry.
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****************************************************************************/
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#ifndef __ARCH_RISC_V_INCLUDE_GAP8_IRQ_H
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#define __ARCH_RISC_V_INCLUDE_GAP8_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <arch/irq.h>
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#include <stdint.h>
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/****************************************************************************
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* Pre-Processor Definitions
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****************************************************************************/
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/* Unique ID in SOC domain */
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/* uDMA data events.
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* Each peripheral has a uDMA_ID.
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* Each peripheral also has RX and TX event ID, which happen to be 2*uDMA_ID
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* and 2*uDMA_ID+1.
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*/
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#define GAP8_EVENT_UDMA_LVDS_RX 0
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#define GAP8_EVENT_UDMA_LVDS_TX 1
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#define GAP8_EVENT_UDMA_SPIM0_RX 2
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#define GAP8_EVENT_UDMA_SPIM0_TX 3
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#define GAP8_EVENT_UDMA_SPIM1_RX 4
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#define GAP8_EVENT_UDMA_SPIM1_TX 5
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#define GAP8_EVENT_UDMA_HYPERBUS_RX 6
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#define GAP8_EVENT_UDMA_HYPERBUS_TX 7
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#define GAP8_EVENT_UDMA_UART_RX 8
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#define GAP8_EVENT_UDMA_UART_TX 9
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#define GAP8_EVENT_UDMA_I2C0_RX 10
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#define GAP8_EVENT_UDMA_I2C0_TX 11
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#define GAP8_EVENT_UDMA_I2C1_RX 12
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#define GAP8_EVENT_UDMA_I2C1_TX 13
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#define GAP8_EVENT_UDMA_TCDM_RX 14
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#define GAP8_EVENT_UDMA_TCDM_TX 15
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#define GAP8_EVENT_UDMA_SAI_CH0 16
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#define GAP8_EVENT_UDMA_SAI_CH1 17
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#define GAP8_EVENT_UDMA_CPI_RX 18
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#define GAP8_UDMA_MAX_EVENT 18
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/* Other events of uDMA peripherals */
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#define GAP8_EVENT_LVDS_GEN0 20
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#define GAP8_EVENT_LVDS_GEN1 21
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#define GAP8_EVENT_SPIM0_EOT 22
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#define GAP8_EVENT_SPIM1_EOT 23
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#define GAP8_EVENT_HYPERBUS_RESERVED 24
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#define GAP8_EVENT_UART_RESERVED 25
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#define GAP8_EVENT_I2C0_ERROR 26
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#define GAP8_EVENT_I2C1_ERROR 27
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#define GAP8_EVENT_I2S_RESERVED 28
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#define GAP8_EVENT_CAM_RESERVED 29
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/* PMU events */
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#define GAP8_EVENT_PMU_CLUSTER_POWER_ON 31
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#define GAP8_EVENT_PMU_CLUSTER_RESERVED0 32
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#define GAP8_EVENT_PMU_CLUSTER_RESERVED1 33
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#define GAP8_EVENT_PMU_CLUSTER_RESERVED2 34
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#define GAP8_EVENT_PMU_CLUSTER_CLOCK_GATING 35
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#define GAP8_EVENT_PMU_DLC_BRIDGE_PICL_OK 36
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#define GAP8_EVENT_PMU_DLC_BRIDGE_SCU_OK 37
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/* Other SOC domain peripheral events */
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#define GAP8_EVENT_PWM0 38
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#define GAP8_EVENT_PWM1 39
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#define GAP8_EVENT_PWM2 40
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#define GAP8_EVENT_PWM3 41
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#define GAP8_EVENT_GPIO 42 /* GPIO group interrupt */
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#define GAP8_EVENT_RTC_APB 43
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#define GAP8_EVENT_RTC 44
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#define GAP8_EVENT_RESERVED0 45
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#define GAP8_EVENT_RESERVED1 46
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#define GAP8_EVENT_RESERVED2 47
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#define GAP8_EVENT_SOC_SW_0 48 /* GAP8 SOC SW Event0 */
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#define GAP8_EVENT_SOC_SW_1 49 /* GAP8 SOC SW Event1 */
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#define GAP8_EVENT_SOC_SW_2 50 /* GAP8 SOC SW Event2 */
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#define GAP8_EVENT_SOC_SW_3 51 /* GAP8 SOC SW Event3 */
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#define GAP8_EVENT_SOC_SW_4 52 /* GAP8 SOC SW Event4 */
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#define GAP8_EVENT_SOC_SW_5 53 /* GAP8 SOC SW Event5 */
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#define GAP8_EVENT_SOC_SW_6 54 /* GAP8 SOC SW Event6 */
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#define GAP8_EVENT_SOC_SW_7 55 /* GAP8 SOC SW Event7 */
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#define GAP8_EVENT_REF32K_CLK_RISE 56 /* Reference 32K Clock event */
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/* FC domain IRQ ID */
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#define GAP8_IRQ_FC_SW_0 0
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#define GAP8_IRQ_FC_SW_1 1
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#define GAP8_IRQ_FC_SW_2 2
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#define GAP8_IRQ_FC_SW_3 3
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#define GAP8_IRQ_FC_SW_4 4
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#define GAP8_IRQ_FC_SW_5 5
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#define GAP8_IRQ_FC_SW_6 6
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#define GAP8_IRQ_FC_SW_7 7
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#define GAP8_IRQ_FC_TIMER_LO 10
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#define GAP8_IRQ_FC_TIMER_HI 11
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#define GAP8_IRQ_FC_UDMA 27
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#define GAP8_IRQ_FC_MPU 28
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#define GAP8_IRQ_FC_UDMA_ERR 29
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#define GAP8_IRQ_FC_HP_0 30
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#define GAP8_IRQ_FC_HP_1 31
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#define GAP8_IRQ_RESERVED 60
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/* Cluster domain IRQ ID */
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/* TODO */
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/* RISCY core exception vectors */
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#define GAP8_IRQ_RST 32
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#define GAP8_IRQ_ILLEGAL 33
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#define GAP8_IRQ_SYSCALL 34
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/* Total number of IRQs.
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* 32 ISRs + reset-handler + illegal-instruction-handler +
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* system-call-handler
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*/
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#define NR_IRQS 35
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/* SOC_EU - SOC domain event unit */
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typedef struct
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{
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volatile uint32_t EVENT; /* event register */
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volatile uint32_t FC_MASK_MSB; /* fc mask MSB register */
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volatile uint32_t FC_MASK_LSB; /* fc mask LSB register */
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volatile uint32_t CL_MASK_MSB; /* cluster mask MSB register */
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volatile uint32_t CL_MASK_LSB; /* cluster mask LSB register */
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volatile uint32_t PR_MASK_MSB; /* propagate mask MSB register */
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volatile uint32_t PR_MASK_LSB; /* propagate mask LSB register */
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volatile uint32_t ERR_MASK_MSB; /* error mask MSB register */
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volatile uint32_t ERR_MASK_LSB; /* error mask LSB register */
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volatile uint32_t TIMER_SEL_HI; /* timer high register */
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volatile uint32_t TIMER_SEL_LO; /* timer low register */
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} soc_eu_reg_t;
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#define SOC_EU ((soc_eu_reg_t *)0x1A106000U)
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/* FCEU - FC domain event unit */
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typedef struct
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{
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volatile uint32_t MASK; /* mask register */
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volatile uint32_t MASK_AND; /* mask-and(clr) register */
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volatile uint32_t MASK_OR; /* mask-or(set) register */
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volatile uint32_t MASK_IRQ; /* irq mask register */
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volatile uint32_t MASK_IRQ_AND; /* irq mask-and(clr) register */
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volatile uint32_t MASK_IRQ_OR; /* irq mask-or(set) register */
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volatile uint32_t STATUS; /* clock Status register */
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volatile uint32_t BUFFER; /* irq pending register */
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volatile uint32_t BUFFER_MASKED; /* buffer masked register */
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volatile uint32_t BUFFER_IRQ_MASKED; /* buffer irq masked register */
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volatile uint32_t BUFFER_CLEAR; /* clear irq pending */
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volatile uint32_t SW_EVENTS_MASK; /* software event mask register */
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volatile uint32_t SW_EVENTS_MASK_AND; /* software event mask and register */
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volatile uint32_t SW_EVENTS_MASK_OR; /* software event mask or register */
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volatile uint32_t EVENT_WAIT; /* event wait register */
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volatile uint32_t EVENT_WAIT_CLEAR; /* event wait clear register */
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volatile uint32_t MASK_SEC_IRQ; /* mask sec irq register */
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} fceu_reg_t;
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#define FCEU ((fceu_reg_t*)0x00204000U)
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/* Current interrupt event ID */
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typedef struct
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{
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volatile uint32_t CURRENT_EVENT; /* current event register */
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} soc_event_reg_t;
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#define SOC_EVENTS ((soc_event_reg_t*)0x00200F00UL)
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/* event trigger and mask */
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typedef struct
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{
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volatile uint32_t TRIGGER_SET[8]; /* trigger set register */
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volatile uint32_t _reserved0[8]; /* Offset: 0x20 (R/W) Empty Registers */
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volatile uint32_t TRIGGER_WAIT[8]; /* trigger wait register */
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volatile uint32_t _reserved1[8]; /* Offset: 0x60 (R/W) Empty Registers */
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volatile uint32_t TRIGGER_CLR[8]; /* trigger clear register */
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} eu_sw_events_trigger_reg_t;
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#define EU_SW_EVNT_TRIG ((eu_sw_events_trigger_reg_t*)0x00204100UL)
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_disable_event
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*
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* Description:
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* Disable the specific event. Note that setting 1 means to disable an
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* event...
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*
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****************************************************************************/
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static inline void up_disable_event(int event)
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{
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if (event >= 32)
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{
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SOC_EU->FC_MASK_MSB |= (1 << (event - 32));
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}
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else
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{
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SOC_EU->FC_MASK_LSB |= (1 << event);
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}
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}
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/****************************************************************************
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* Name: up_enable_event
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*
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* Description:
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* Enable the specific event. Note that setting 0 means to enable an
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* event...
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*
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****************************************************************************/
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static inline void up_enable_event(int event)
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{
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if (event >= 32)
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{
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SOC_EU->FC_MASK_MSB &= ~(1 << (event - 32));
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}
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else
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{
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SOC_EU->FC_MASK_LSB &= ~(1 << event);
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}
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}
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/****************************************************************************
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* Name: up_disable_irq
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*
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* Description:
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* Disable the IRQ specified by 'irq'. Mind the Machine privilege.
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*
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****************************************************************************/
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static inline void up_disable_irq(int irq)
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{
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FCEU->MASK_IRQ_AND = (1UL << irq);
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}
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/****************************************************************************
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* Name: up_enable_irq
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*
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* Description:
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* Enable the IRQ specified by 'irq'. Mind the Machine privilege.
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*
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****************************************************************************/
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static inline void up_enable_irq(int irq)
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{
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FCEU->MASK_IRQ_OR = (1 << irq);
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}
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/****************************************************************************
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* Name: up_ack_irq
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*
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* Description:
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* Acknowledge the IRQ
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*
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****************************************************************************/
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static inline void up_ack_irq(int irq)
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{
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}
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/****************************************************************************
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* Name: _current_privilege
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*
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* Description:
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* Get the current privilege mode. 0x0 for user mode, and 0x3 for machine
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* mode.
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*
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****************************************************************************/
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static inline uint32_t _current_privilege(void)
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{
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uint32_t result;
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asm volatile ("csrr %0, 0xC10" : "=r" (result));
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return result;
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}
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/****************************************************************************
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* Name: up_irq_save
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*
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* Description:
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* Disable interrupt and return the current interrupt state.
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*
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****************************************************************************/
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static inline irqstate_t up_irq_save(void)
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{
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irqstate_t oldstat;
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irqstate_t newstat;
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if (_current_privilege())
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{
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/* Machine mode: Unset MIE and UIE */
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asm volatile ("csrr %0, 0x300": "=r" (oldstat));
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newstat = oldstat & ~(0x9);
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asm volatile("csrw 0x300, %0" : /* no output */ : "r" (newstat));
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}
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else
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{
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/* User mode: Unset UIE */
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asm volatile ("csrr %0, 0x000": "=r" (oldstat));
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newstat = oldstat & ~(1L << 0);
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asm volatile("csrw 0x000, %0" : /* no output */ : "r" (newstat));
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}
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return oldstat;
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}
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/****************************************************************************
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* Name: up_irq_restore
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*
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* Description:
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* Restore previous IRQ mask state
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*
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****************************************************************************/
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static inline void up_irq_restore(uint32_t pri)
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{
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if (_current_privilege())
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{
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/* Machine mode - mstatus */
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asm volatile("csrw 0x300, %0" : /* no output */ : "r" (pri));
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}
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else
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{
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/* User mode - ustatus */
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asm volatile("csrw 0x000, %0" : /* no output */ : "r" (pri));
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}
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}
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/****************************************************************************
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* Name: up_irq_enable
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*
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* Description:
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* Return the current interrupt state and enable interrupts
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*
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****************************************************************************/
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static inline irqstate_t up_irq_enable(void)
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{
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irqstate_t oldstat;
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irqstate_t newstat;
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if (_current_privilege())
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{
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/* Machine mode: Set MIE and UIE */
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asm volatile ("csrr %0, 0x300": "=r" (oldstat));
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newstat = oldstat | (0x9);
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asm volatile("csrw 0x300, %0" : /* no output */ : "r" (newstat));
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}
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else
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{
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/* User mode: Set UIE */
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asm volatile ("csrr %0, 0x000": "=r" (oldstat));
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newstat = oldstat | (1L << 0);
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asm volatile("csrw 0x000, %0" : /* no output */ : "r" (newstat));
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}
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return oldstat;
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}
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/****************************************************************************
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* Name: gap8_sleep_wait_sw_evnt
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*
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* Description:
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* Sleep on specific event.
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*
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****************************************************************************/
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static inline void gap8_sleep_wait_sw_evnt(uint32_t event_mask)
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{
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FCEU->MASK_OR = event_mask;
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__builtin_pulp_event_unit_read((void *)&FCEU->EVENT_WAIT_CLEAR, 0);
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FCEU->MASK_AND = event_mask;
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}
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_RISC_V_INCLUDE_GAP8_IRQ_H */
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