1333 lines
38 KiB
C
1333 lines
38 KiB
C
/****************************************************************************
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* arch/arm/src/s32k1xx/s32k1xx_serial.c
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <unistd.h>
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#include <string.h>
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#include <errno.h>
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#include <debug.h>
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#ifdef CONFIG_SERIAL_TERMIOS
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# include <termios.h>
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#endif
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <nuttx/init.h>
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#include <nuttx/power/pm.h>
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#include <nuttx/fs/ioctl.h>
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#include <nuttx/serial/serial.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "up_arch.h"
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#include "up_internal.h"
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#include "hardware/s32k1xx_lpuart.h"
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#include "hardware/s32k1xx_pinmux.h"
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#include "s32k1xx_config.h"
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#include "s32k1xx_pin.h"
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#include "s32k1xx_lowputc.h"
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#ifdef USE_SERIALDRIVER
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Which LPUART with be tty0/console and which tty1-7? The console will
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* always be ttyS0. If there is no console then will use the lowest
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* numbered LPUART.
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*/
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/* First pick the console and ttys0. This could be any of LPUART0-2 */
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#if defined(CONFIG_LPUART0_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_uart0port /* LPUART0 is console */
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# define TTYS0_DEV g_uart0port /* LPUART0 is ttyS0 */
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# define UART1_ASSIGNED 1
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#elif defined(CONFIG_LPUART1_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_uart1port /* LPUART1 is console */
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# define TTYS0_DEV g_uart1port /* LPUART1 is ttyS0 */
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# define UART2_ASSIGNED 1
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#elif defined(CONFIG_LPUART2_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_uart2port /* LPUART2 is console */
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# define TTYS0_DEV g_uart2port /* LPUART2 is ttyS0 */
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# define UART3_ASSIGNED 1
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#else
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# undef CONSOLE_DEV /* No console */
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# if defined(CONFIG_S32K1XX_LPUART0)
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# define TTYS0_DEV g_uart0port /* LPUART0 is ttyS0 */
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# define UART1_ASSIGNED 1
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# elif defined(CONFIG_S32K1XX_LPUART1)
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# define TTYS0_DEV g_uart1port /* LPUART1 is ttyS0 */
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# define UART2_ASSIGNED 1
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# elif defined(CONFIG_S32K1XX_LPUART2)
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# define TTYS0_DEV g_uart2port /* LPUART2 is ttyS0 */
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# define UART3_ASSIGNED 1
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# endif
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#endif
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/* Pick ttys1. This could be any of LPUART0-2 excluding the console UART.
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* One of LPUART0-8 could be the console; one of UART0-2 has already been
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* assigned to ttys0.
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*/
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#if defined(CONFIG_S32K1XX_LPUART0) && !defined(UART1_ASSIGNED)
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# define TTYS1_DEV g_uart0port /* LPUART0 is ttyS1 */
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# define UART1_ASSIGNED 1
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#elif defined(CONFIG_S32K1XX_LPUART1) && !defined(UART2_ASSIGNED)
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# define TTYS1_DEV g_uart1port /* LPUART1 is ttyS1 */
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# define UART2_ASSIGNED 1
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#elif defined(CONFIG_S32K1XX_LPUART2) && !defined(UART3_ASSIGNED)
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# define TTYS1_DEV g_uart2port /* LPUART2 is ttyS1 */
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# define UART3_ASSIGNED 1
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#endif
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/* Pick ttys2. This could be one of LPUART0-2. It can't be LPUART0 because
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* that was either assigned as ttyS0 or ttys1. One of LPUART0-2 could be the
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* console. One of UART1-2 has already been assigned to ttys0 or ttyS1.
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*/
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#if defined(CONFIG_S32K1XX_LPUART1) && !defined(UART2_ASSIGNED)
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# define TTYS2_DEV g_uart1port /* LPUART1 is ttyS2 */
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# define UART2_ASSIGNED 1
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#elif defined(CONFIG_S32K1XX_LPUART2) && !defined(UART3_ASSIGNED)
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# define TTYS2_DEV g_uart2port /* LPUART2 is ttyS2 */
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# define UART3_ASSIGNED 1
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#endif
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/* Power management definitions */
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#if defined(CONFIG_PM) && !defined(CONFIG_S32K1XX_PM_SERIAL_ACTIVITY)
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# define CONFIG_S32K1XX_PM_SERIAL_ACTIVITY 10
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#endif
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#if defined(CONFIG_PM)
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# define PM_IDLE_DOMAIN 0 /* Revisit */
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct s32k1xx_uart_s
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{
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uint32_t uartbase; /* Base address of UART registers */
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uint32_t baud; /* Configured baud */
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uint32_t ie; /* Saved enabled interrupts */
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uint8_t irq; /* IRQ associated with this UART */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (7 or 8) */
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#if defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)
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uint8_t inviflow:1; /* Invert RTS sense */
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const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */
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#endif
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uint8_t stopbits2:1; /* 1: Configure with 2 stop bits vs 1 */
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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uint8_t iflow:1; /* input flow control (RTS) enabled */
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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uint8_t oflow:1; /* output flow control (CTS) enabled */
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#endif
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#ifdef CONFIG_SERIAL_RS485CONTROL
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uint8_t rs485mode:1; /* We are in RS485 (RTS on TX) mode */
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#endif
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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static inline uint32_t s32k1xx_serialin(struct s32k1xx_uart_s *priv,
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uint32_t offset);
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static inline void s32k1xx_serialout(struct s32k1xx_uart_s *priv,
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uint32_t offset, uint32_t value);
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static inline void s32k1xx_disableuartint(struct s32k1xx_uart_s *priv,
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uint32_t *ie);
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static inline void s32k1xx_restoreuartint(struct s32k1xx_uart_s *priv,
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uint32_t ie);
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static int s32k1xx_setup(struct uart_dev_s *dev);
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static void s32k1xx_shutdown(struct uart_dev_s *dev);
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static int s32k1xx_attach(struct uart_dev_s *dev);
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static void s32k1xx_detach(struct uart_dev_s *dev);
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static int s32k1xx_interrupt(int irq, void *context, FAR void *arg);
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static int s32k1xx_ioctl(struct file *filep, int cmd, unsigned long arg);
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static int s32k1xx_receive(struct uart_dev_s *dev, uint32_t *status);
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static void s32k1xx_rxint(struct uart_dev_s *dev, bool enable);
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static bool s32k1xx_rxavailable(struct uart_dev_s *dev);
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static void s32k1xx_send(struct uart_dev_s *dev, int ch);
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static void s32k1xx_txint(struct uart_dev_s *dev, bool enable);
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static bool s32k1xx_txready(struct uart_dev_s *dev);
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static bool s32k1xx_txempty(struct uart_dev_s *dev);
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#ifdef CONFIG_PM
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static void up_pm_notify(struct pm_callback_s *cb, int dowmin,
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enum pm_state_e pmstate);
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static int up_pm_prepare(struct pm_callback_s *cb, int domain,
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enum pm_state_e pmstate);
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* Serial driver UART operations */
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static const struct uart_ops_s g_uart_ops =
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{
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.setup = s32k1xx_setup,
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.shutdown = s32k1xx_shutdown,
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.attach = s32k1xx_attach,
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.detach = s32k1xx_detach,
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.ioctl = s32k1xx_ioctl,
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.receive = s32k1xx_receive,
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.rxint = s32k1xx_rxint,
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.rxavailable = s32k1xx_rxavailable,
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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.rxflowcontrol = NULL,
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#endif
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.send = s32k1xx_send,
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.txint = s32k1xx_txint,
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.txready = s32k1xx_txready,
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.txempty = s32k1xx_txempty,
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};
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/* I/O buffers */
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#ifdef CONFIG_S32K1XX_LPUART0
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static char g_uart0rxbuffer[CONFIG_LPUART0_RXBUFSIZE];
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static char g_uart0txbuffer[CONFIG_LPUART0_TXBUFSIZE];
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#endif
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#ifdef CONFIG_S32K1XX_LPUART1
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static char g_uart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE];
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static char g_uart1txbuffer[CONFIG_LPUART1_TXBUFSIZE];
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#endif
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#ifdef CONFIG_S32K1XX_LPUART2
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static char g_uart2rxbuffer[CONFIG_LPUART2_RXBUFSIZE];
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static char g_uart2txbuffer[CONFIG_LPUART2_TXBUFSIZE];
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#endif
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/* This describes the state of the S32K1XX lpuart0 port. */
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#ifdef CONFIG_S32K1XX_LPUART0
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static struct s32k1xx_uart_s g_uart0priv =
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{
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.uartbase = S32K1XX_LPUART0_BASE,
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.baud = CONFIG_LPUART0_BAUD,
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.irq = S32K1XX_IRQ_LPUART0,
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.parity = CONFIG_LPUART0_PARITY,
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.bits = CONFIG_LPUART0_BITS,
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.stopbits2 = CONFIG_LPUART0_2STOP,
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#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART0_OFLOWCONTROL)
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.oflow = 1,
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.cts_gpio = GPIO_LPUART0_CTS,
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#endif
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#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART0_IFLOWCONTROL)
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.iflow = 1,
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#endif
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# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART0_RS485RTSCONTROL)) \
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|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART0_IFLOWCONTROL)))
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.rts_gpio = GPIO_LPUART0_RTS,
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#endif
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#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
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&& defined(CONFIG_LPUART0_INVERTIFLOWCONTROL))
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.inviflow = 1,
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#endif
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#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART0_RS485RTSCONTROL)
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.rs485mode = 1,
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#endif
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};
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static struct uart_dev_s g_uart0port =
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{
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.recv =
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{
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.size = CONFIG_LPUART0_RXBUFSIZE,
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.buffer = g_uart0rxbuffer,
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},
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.xmit =
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{
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.size = CONFIG_LPUART0_TXBUFSIZE,
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.buffer = g_uart0txbuffer,
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},
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.ops = &g_uart_ops,
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.priv = &g_uart0priv,
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};
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#endif
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/* This describes the state of the S32K1XX lpuart1 port. */
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#ifdef CONFIG_S32K1XX_LPUART1
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static struct s32k1xx_uart_s g_uart1priv =
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{
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.uartbase = S32K1XX_LPUART1_BASE,
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.baud = CONFIG_LPUART1_BAUD,
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.irq = S32K1XX_IRQ_LPUART1,
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.parity = CONFIG_LPUART1_PARITY,
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.bits = CONFIG_LPUART1_BITS,
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.stopbits2 = CONFIG_LPUART1_2STOP,
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#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
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.oflow = 1,
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.cts_gpio = GPIO_LPUART1_CTS,
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#endif
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#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
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.iflow = 1,
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#endif
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# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) \
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|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)))
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.rts_gpio = GPIO_LPUART1_RTS,
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#endif
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#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
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&& defined(CONFIG_LPUART1_INVERTIFLOWCONTROL))
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.inviflow = 1,
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#endif
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#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)
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.rs485mode = 1,
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#endif
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};
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static struct uart_dev_s g_uart1port =
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{
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.recv =
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{
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.size = CONFIG_LPUART1_RXBUFSIZE,
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.buffer = g_uart1rxbuffer,
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},
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.xmit =
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{
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.size = CONFIG_LPUART1_TXBUFSIZE,
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.buffer = g_uart1txbuffer,
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},
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.ops = &g_uart_ops,
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.priv = &g_uart1priv,
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};
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#endif
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#ifdef CONFIG_S32K1XX_LPUART2
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static struct s32k1xx_uart_s g_uart2priv =
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{
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.uartbase = S32K1XX_LPUART2_BASE,
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.baud = CONFIG_LPUART2_BAUD,
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.irq = S32K1XX_IRQ_LPUART2,
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.parity = CONFIG_LPUART2_PARITY,
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.bits = CONFIG_LPUART2_BITS,
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.stopbits2 = CONFIG_LPUART2_2STOP,
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#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL)
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.oflow = 1,
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.cts_gpio = GPIO_LPUART2_CTS,
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#endif
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#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)
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.iflow = 1,
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#endif
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# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) \
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|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)))
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.rts_gpio = GPIO_LPUART2_RTS,
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#endif
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#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
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&& defined(CONFIG_LPUART2_INVERTIFLOWCONTROL))
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.inviflow = 1,
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#endif
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#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)
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.rs485mode = 1,
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#endif
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};
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static struct uart_dev_s g_uart2port =
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{
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.recv =
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{
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.size = CONFIG_LPUART2_RXBUFSIZE,
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.buffer = g_uart2rxbuffer,
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},
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.xmit =
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{
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.size = CONFIG_LPUART2_TXBUFSIZE,
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.buffer = g_uart2txbuffer,
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},
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.ops = &g_uart_ops,
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.priv = &g_uart2priv,
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};
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#endif
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#ifdef CONFIG_PM
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static struct pm_callback_s g_serial_pmcb =
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{
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.notify = up_pm_notify,
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.prepare = up_pm_prepare,
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};
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: s32k1xx_serialin
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****************************************************************************/
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static inline uint32_t s32k1xx_serialin(struct s32k1xx_uart_s *priv,
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uint32_t offset)
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{
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return getreg32(priv->uartbase + offset);
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}
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|
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/****************************************************************************
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* Name: s32k1xx_serialout
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****************************************************************************/
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static inline void s32k1xx_serialout(struct s32k1xx_uart_s *priv, uint32_t offset,
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uint32_t value)
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{
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putreg32(value, priv->uartbase + offset);
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}
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|
|
/****************************************************************************
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* Name: s32k1xx_disableuartint
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****************************************************************************/
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|
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static inline void s32k1xx_disableuartint(struct s32k1xx_uart_s *priv,
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uint32_t *ie)
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{
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irqstate_t flags;
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uint32_t regval;
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flags = spin_lock_irqsave();
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regval = s32k1xx_serialin(priv, S32K1XX_LPUART_CTRL_OFFSET);
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/* Return the current Rx and Tx interrupt state */
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|
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if (ie != NULL)
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{
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*ie = regval & LPUART_ALL_INTS;
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}
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regval &= ~LPUART_ALL_INTS;
|
|
s32k1xx_serialout(priv, S32K1XX_LPUART_CTRL_OFFSET, regval);
|
|
spin_unlock_irqrestore(flags);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_restoreuartint
|
|
****************************************************************************/
|
|
|
|
static inline void s32k1xx_restoreuartint(struct s32k1xx_uart_s *priv,
|
|
uint32_t ie)
|
|
{
|
|
irqstate_t flags;
|
|
uint32_t regval;
|
|
|
|
/* Enable/disable any interrupts that are currently disabled but should be
|
|
* enabled/disabled.
|
|
*/
|
|
|
|
flags = spin_lock_irqsave();
|
|
regval = s32k1xx_serialin(priv, S32K1XX_LPUART_CTRL_OFFSET);
|
|
regval &= ~LPUART_ALL_INTS;
|
|
regval |= ie;
|
|
s32k1xx_serialout(priv, S32K1XX_LPUART_CTRL_OFFSET, regval);
|
|
spin_unlock_irqrestore(flags);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_setup
|
|
*
|
|
* Description:
|
|
* Configure the UART baud, bits, parity, fifos, etc. This
|
|
* method is called the first time that the serial port is
|
|
* opened.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int s32k1xx_setup(struct uart_dev_s *dev)
|
|
{
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
#ifndef CONFIG_SUPPRESS_LPUART_CONFIG
|
|
struct uart_config_s config =
|
|
{
|
|
0
|
|
};
|
|
int ret;
|
|
|
|
/* Configure the UART */
|
|
|
|
config.baud = priv->baud; /* Configured baud */
|
|
config.parity = priv->parity; /* 0=none, 1=odd, 2=even */
|
|
config.bits = priv->bits; /* Number of bits (5-9) */
|
|
config.stopbits2 = priv->stopbits2; /* true: Configure with 2 stop bits instead of 1 */
|
|
#ifdef CONFIG_SERIAL_IFLOWCONTROL
|
|
config.usects = priv->iflow; /* Flow control on inbound side */
|
|
#endif
|
|
#ifdef CONFIG_SERIAL_OFLOWCONTROL
|
|
config.userts = priv->oflow; /* Flow control on outbound side */
|
|
#endif
|
|
#ifdef CONFIG_SERIAL_RS485CONTROL
|
|
config.users485 = priv->rs485mode; /* Switch into RS485 mode */
|
|
#endif
|
|
#if defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)
|
|
config.invrts = priv->inviflow; /* Inversion of outbound flow control */
|
|
#endif
|
|
|
|
ret = s32k1xx_lpuart_configure(priv->uartbase, &config);
|
|
|
|
priv->ie = s32k1xx_serialin(priv, S32K1XX_LPUART_CTRL_OFFSET) & LPUART_ALL_INTS;
|
|
return ret;
|
|
|
|
#else
|
|
priv->ie = s32k1xx_serialin(priv, S32K1XX_LPUART_CTRL_OFFSET) & LPUART_ALL_INTS;
|
|
return OK;
|
|
#endif
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_shutdown
|
|
*
|
|
* Description:
|
|
* Disable the UART. This method is called when the serial
|
|
* port is closed
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void s32k1xx_shutdown(struct uart_dev_s *dev)
|
|
{
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
|
|
/* Disable the UART */
|
|
|
|
s32k1xx_serialout(priv, S32K1XX_LPUART_GLOBAL_OFFSET, LPUART_GLOBAL_RST);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_attach
|
|
*
|
|
* Description:
|
|
* Configure the UART to operation in interrupt driven mode. This method
|
|
* is called when the serial port is opened. Normally, this is just after
|
|
* the setup() method is called, however, the serial console may operate
|
|
* in a non-interrupt driven mode during the boot phase.
|
|
*
|
|
* RX and TX interrupts are not enabled when by the attach method (unless
|
|
* the hardware supports multiple levels of interrupt enabling). The RX
|
|
* and TX interrupts are not enabled until the txint() and rxint() methods
|
|
* are called.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int s32k1xx_attach(struct uart_dev_s *dev)
|
|
{
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
int ret;
|
|
|
|
/* Attach and enable the IRQ */
|
|
|
|
ret = irq_attach(priv->irq, s32k1xx_interrupt, dev);
|
|
if (ret == OK)
|
|
{
|
|
/* Enable the interrupt (RX and TX interrupts are still disabled
|
|
* in the UART
|
|
*/
|
|
|
|
up_enable_irq(priv->irq);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_detach
|
|
*
|
|
* Description:
|
|
* Detach UART interrupts. This method is called when the serial port is
|
|
* closed normally just before the shutdown method is called. The
|
|
* exception is the serial console which is never shutdown.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void s32k1xx_detach(struct uart_dev_s *dev)
|
|
{
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
|
|
up_disable_irq(priv->irq);
|
|
irq_detach(priv->irq);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_interrupt (and front-ends)
|
|
*
|
|
* Description:
|
|
* This is the common UART interrupt handler. It should cal
|
|
* uart_transmitchars or uart_receivechar to perform the appropriate data
|
|
* transfers.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int s32k1xx_interrupt(int irq, void *context, FAR void *arg)
|
|
{
|
|
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
|
|
struct s32k1xx_uart_s *priv;
|
|
uint32_t usr;
|
|
int passes = 0;
|
|
bool handled;
|
|
|
|
DEBUGASSERT(dev != NULL && dev->priv != NULL);
|
|
priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
|
|
#if defined(CONFIG_PM) && CONFIG_S32K1XX_PM_SERIAL_ACTIVITY > 0
|
|
/* Report serial activity to the power management logic */
|
|
|
|
pm_activity(PM_IDLE_DOMAIN, CONFIG_S32K1XX_PM_SERIAL_ACTIVITY);
|
|
#endif
|
|
|
|
/* Loop until there are no characters to be transferred or,
|
|
* until we have been looping for a long time.
|
|
*/
|
|
|
|
handled = true;
|
|
for (passes = 0; passes < 256 && handled; passes++)
|
|
{
|
|
handled = false;
|
|
|
|
/* Get the current UART status and check for loop
|
|
* termination conditions
|
|
*/
|
|
|
|
usr = s32k1xx_serialin(priv, S32K1XX_LPUART_STAT_OFFSET);
|
|
usr &= (LPUART_STAT_RDRF | LPUART_STAT_TC | LPUART_STAT_OR |
|
|
LPUART_STAT_FE);
|
|
|
|
/* Clear serial overrun and framing errors */
|
|
|
|
if ((usr & LPUART_STAT_OR) != 0)
|
|
{
|
|
s32k1xx_serialout(priv, S32K1XX_LPUART_STAT_OFFSET, LPUART_STAT_OR);
|
|
}
|
|
|
|
if ((usr & LPUART_STAT_FE) != 0)
|
|
{
|
|
s32k1xx_serialout(priv, S32K1XX_LPUART_STAT_OFFSET, LPUART_STAT_FE);
|
|
}
|
|
|
|
/* Handle incoming, receive bytes */
|
|
|
|
if ((usr & LPUART_STAT_RDRF) != 0 &&
|
|
(priv->ie & LPUART_CTRL_RIE) != 0)
|
|
{
|
|
uart_recvchars(dev);
|
|
handled = true;
|
|
}
|
|
|
|
/* Handle outgoing, transmit bytes */
|
|
|
|
if ((usr & LPUART_STAT_TC) != 0 &&
|
|
(priv->ie & LPUART_CTRL_TCIE) != 0)
|
|
{
|
|
uart_xmitchars(dev);
|
|
handled = true;
|
|
}
|
|
}
|
|
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_ioctl
|
|
*
|
|
* Description:
|
|
* All ioctl calls will be routed through this method
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int s32k1xx_ioctl(struct file *filep, int cmd, unsigned long arg)
|
|
{
|
|
#if defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || defined(CONFIG_SERIAL_TERMIOS)
|
|
struct inode *inode = filep->f_inode;
|
|
struct uart_dev_s *dev = inode->i_private;
|
|
#endif
|
|
int ret = OK;
|
|
|
|
switch (cmd)
|
|
{
|
|
#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
|
|
case TIOCSERGSTRUCT:
|
|
{
|
|
struct s32k1xx_uart_s *user = (struct s32k1xx_uart_s *)arg;
|
|
if (!user)
|
|
{
|
|
ret = -EINVAL;
|
|
}
|
|
else
|
|
{
|
|
memcpy(user, dev, sizeof(struct s32k1xx_uart_s));
|
|
}
|
|
}
|
|
break;
|
|
#endif
|
|
|
|
#ifdef CONFIG_SERIAL_TERMIOS
|
|
case TCGETS:
|
|
{
|
|
struct termios *termiosp = (struct termios *)arg;
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
|
|
if (!termiosp)
|
|
{
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
/* Return baud */
|
|
|
|
cfsetispeed(termiosp, priv->baud);
|
|
|
|
/* Return parity */
|
|
|
|
termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
|
|
((priv->parity == 1) ? PARODD : 0);
|
|
|
|
/* Return stop bits */
|
|
|
|
termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0;
|
|
|
|
/* Return flow control */
|
|
|
|
#ifdef CONFIG_SERIAL_OFLOWCONTROL
|
|
termiosp->c_cflag |= ((priv->oflow) ? CCTS_OFLOW : 0);
|
|
#endif
|
|
#ifdef CONFIG_SERIAL_IFLOWCONTROL
|
|
termiosp->c_cflag |= ((priv->iflow) ? CRTS_IFLOW : 0);
|
|
#endif
|
|
/* Return number of bits */
|
|
|
|
switch (priv->bits)
|
|
{
|
|
case 5:
|
|
termiosp->c_cflag |= CS5;
|
|
break;
|
|
|
|
case 6:
|
|
termiosp->c_cflag |= CS6;
|
|
break;
|
|
|
|
case 7:
|
|
termiosp->c_cflag |= CS7;
|
|
break;
|
|
|
|
default:
|
|
case 8:
|
|
termiosp->c_cflag |= CS8;
|
|
break;
|
|
|
|
case 9:
|
|
termiosp->c_cflag |= CS8 /* CS9 */;
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case TCSETS:
|
|
{
|
|
struct termios *termiosp = (struct termios *)arg;
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
uint32_t baud;
|
|
uint32_t ie;
|
|
uint8_t parity;
|
|
uint8_t nbits;
|
|
bool stop2;
|
|
|
|
if ((!termiosp)
|
|
#ifdef CONFIG_SERIAL_OFLOWCONTROL
|
|
|| ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0))
|
|
#endif
|
|
#ifdef CONFIG_SERIAL_IFLOWCONTROL
|
|
|| ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0))
|
|
#endif
|
|
)
|
|
{
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
/* Decode baud. */
|
|
|
|
ret = OK;
|
|
baud = cfgetispeed(termiosp);
|
|
|
|
/* Decode number of bits */
|
|
|
|
switch (termiosp->c_cflag & CSIZE)
|
|
{
|
|
case CS5:
|
|
nbits = 5;
|
|
break;
|
|
|
|
case CS6:
|
|
nbits = 6;
|
|
break;
|
|
|
|
case CS7:
|
|
nbits = 7;
|
|
break;
|
|
|
|
case CS8:
|
|
nbits = 8;
|
|
break;
|
|
#if 0
|
|
case CS9:
|
|
nbits = 9;
|
|
break;
|
|
#endif
|
|
default:
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
/* Decode parity */
|
|
|
|
if ((termiosp->c_cflag & PARENB) != 0)
|
|
{
|
|
parity = (termiosp->c_cflag & PARODD) ? 1 : 2;
|
|
}
|
|
else
|
|
{
|
|
parity = 0;
|
|
}
|
|
|
|
/* Decode stop bits */
|
|
|
|
stop2 = (termiosp->c_cflag & CSTOPB) != 0;
|
|
|
|
/* Verify that all settings are valid before committing */
|
|
|
|
if (ret == OK)
|
|
{
|
|
/* Commit */
|
|
|
|
priv->baud = baud;
|
|
priv->parity = parity;
|
|
priv->bits = nbits;
|
|
priv->stopbits2 = stop2;
|
|
#ifdef CONFIG_SERIAL_OFLOWCONTROL
|
|
priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0;
|
|
#endif
|
|
#ifdef CONFIG_SERIAL_IFLOWCONTROL
|
|
priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0;
|
|
#endif
|
|
/* effect the changes immediately - note that we do not
|
|
* implement TCSADRAIN / TCSAFLUSH
|
|
*/
|
|
|
|
s32k1xx_disableuartint(priv, &ie);
|
|
ret = s32k1xx_setup(dev);
|
|
|
|
/* Restore the interrupt state */
|
|
|
|
s32k1xx_restoreuartint(priv, ie);
|
|
priv->ie = ie;
|
|
}
|
|
}
|
|
break;
|
|
#endif /* CONFIG_SERIAL_TERMIOS */
|
|
|
|
#ifdef CONFIG_S32K1XX_LPUART_INVERT
|
|
case TIOCSINVERT:
|
|
{
|
|
uint32_t ctrl;
|
|
uint32_t stat;
|
|
uint32_t regval;
|
|
irqstate_t flags;
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
|
|
flags = spin_lock_irqsave();
|
|
ctrl = s32k1xx_serialin(priv, S32K1XX_LPUART_CTRL_OFFSET);
|
|
stat = s32k1xx_serialin(priv, S32K1XX_LPUART_STAT_OFFSET);
|
|
regval = ctrl;
|
|
|
|
/* {R|T}XINV bit field can only be written when the receiver is disabled (RE=0). */
|
|
|
|
regval &= ~LPUART_CTRL_RE;
|
|
|
|
s32k1xx_serialout(priv, S32K1XX_LPUART_CTRL_OFFSET, regval);
|
|
|
|
/* Enable/disable signal inversion. */
|
|
|
|
if (arg & SER_INVERT_ENABLED_RX)
|
|
{
|
|
stat |= LPUART_STAT_RXINV;
|
|
}
|
|
else
|
|
{
|
|
stat &= ~LPUART_STAT_RXINV;
|
|
}
|
|
|
|
if (arg & SER_INVERT_ENABLED_TX)
|
|
{
|
|
ctrl |= LPUART_CTRL_TXINV;
|
|
}
|
|
else
|
|
{
|
|
ctrl &= ~LPUART_CTRL_TXINV;
|
|
}
|
|
|
|
s32k1xx_serialout(priv, S32K1XX_LPUART_STAT_OFFSET, stat);
|
|
s32k1xx_serialout(priv, S32K1XX_LPUART_CTRL_OFFSET, ctrl);
|
|
|
|
spin_unlock_irqrestore(flags);
|
|
}
|
|
break;
|
|
#endif
|
|
|
|
case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
|
|
case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
|
|
default:
|
|
ret = -ENOTTY;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_receive
|
|
*
|
|
* Description:
|
|
* Called (usually) from the interrupt level to receive one
|
|
* character from the UART. Error bits associated with the
|
|
* receipt are provided in the return 'status'.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int s32k1xx_receive(struct uart_dev_s *dev, uint32_t *status)
|
|
{
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
uint32_t rxd;
|
|
|
|
rxd = s32k1xx_serialin(priv, S32K1XX_LPUART_DATA_OFFSET);
|
|
*status = rxd >> LPUART_DATA_STATUS_SHIFT;
|
|
return (rxd & LPUART_DATA_MASK) >> LPUART_DATA_SHIFT;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_rxint
|
|
*
|
|
* Description:
|
|
* Call to enable or disable RX interrupts
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void s32k1xx_rxint(struct uart_dev_s *dev, bool enable)
|
|
{
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
irqstate_t flags;
|
|
uint32_t regval;
|
|
|
|
/* Enable interrupts for data available at Rx */
|
|
|
|
flags = spin_lock_irqsave();
|
|
if (enable)
|
|
{
|
|
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
|
priv->ie |= LPUART_CTRL_RIE | LPUART_CTRL_FEIE | LPUART_CTRL_ORIE;
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
priv->ie &= ~(LPUART_CTRL_RIE | LPUART_CTRL_FEIE | LPUART_CTRL_ORIE);
|
|
}
|
|
|
|
regval = s32k1xx_serialin(priv, S32K1XX_LPUART_CTRL_OFFSET);
|
|
regval &= ~LPUART_ALL_INTS;
|
|
regval |= priv->ie;
|
|
s32k1xx_serialout(priv, S32K1XX_LPUART_CTRL_OFFSET, regval);
|
|
spin_unlock_irqrestore(flags);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_rxavailable
|
|
*
|
|
* Description:
|
|
* Return true if the receive fifo is not empty
|
|
*
|
|
****************************************************************************/
|
|
|
|
static bool s32k1xx_rxavailable(struct uart_dev_s *dev)
|
|
{
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
uint32_t regval;
|
|
|
|
/* Return true is data is ready in the Rx FIFO */
|
|
|
|
regval = s32k1xx_serialin(priv, S32K1XX_LPUART_STAT_OFFSET);
|
|
return ((regval & LPUART_STAT_RDRF) != 0);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_send
|
|
*
|
|
* Description:
|
|
* This method will send one byte on the UART
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void s32k1xx_send(struct uart_dev_s *dev, int ch)
|
|
{
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
s32k1xx_serialout(priv, S32K1XX_LPUART_DATA_OFFSET, (uint32_t)ch);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_txint
|
|
*
|
|
* Description:
|
|
* Call to enable or disable TX interrupts
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void s32k1xx_txint(struct uart_dev_s *dev, bool enable)
|
|
{
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
irqstate_t flags;
|
|
uint32_t regval;
|
|
|
|
/* Enable interrupt for TX complete */
|
|
|
|
flags = spin_lock_irqsave();
|
|
if (enable)
|
|
{
|
|
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
|
priv->ie |= LPUART_CTRL_TCIE;
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
priv->ie &= ~LPUART_CTRL_TCIE;
|
|
}
|
|
|
|
regval = s32k1xx_serialin(priv, S32K1XX_LPUART_CTRL_OFFSET);
|
|
regval &= ~LPUART_ALL_INTS;
|
|
regval |= priv->ie;
|
|
s32k1xx_serialout(priv, S32K1XX_LPUART_CTRL_OFFSET, regval);
|
|
spin_unlock_irqrestore(flags);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_txready
|
|
*
|
|
* Description:
|
|
* Return true if the transmit is completed
|
|
*
|
|
****************************************************************************/
|
|
|
|
static bool s32k1xx_txready(struct uart_dev_s *dev)
|
|
{
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
uint32_t regval;
|
|
|
|
regval = s32k1xx_serialin(priv, S32K1XX_LPUART_STAT_OFFSET);
|
|
return ((regval & LPUART_STAT_TC) != 0);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_txempty
|
|
*
|
|
* Description:
|
|
* Return true if the transmit reg is empty
|
|
*
|
|
****************************************************************************/
|
|
|
|
static bool s32k1xx_txempty(struct uart_dev_s *dev)
|
|
{
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)dev->priv;
|
|
uint32_t regval;
|
|
|
|
regval = s32k1xx_serialin(priv, S32K1XX_LPUART_STAT_OFFSET);
|
|
return ((regval & LPUART_STAT_TDRE) != 0);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: up_pm_notify
|
|
*
|
|
* Description:
|
|
* Notify the driver of new power state. This callback is called after
|
|
* all drivers have had the opportunity to prepare for the new power state.
|
|
*
|
|
* Input Parameters:
|
|
*
|
|
* cb - Returned to the driver. The driver version of the callback
|
|
* structure may include additional, driver-specific state data at
|
|
* the end of the structure.
|
|
*
|
|
* pmstate - Identifies the new PM state
|
|
*
|
|
* Returned Value:
|
|
* None - The driver already agreed to transition to the low power
|
|
* consumption state when when it returned OK to the prepare() call.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_PM
|
|
static void up_pm_notify(struct pm_callback_s *cb, int domain,
|
|
enum pm_state_e pmstate)
|
|
{
|
|
switch (pmstate)
|
|
{
|
|
case(PM_NORMAL):
|
|
{
|
|
/* Logic for PM_NORMAL goes here */
|
|
|
|
}
|
|
break;
|
|
|
|
case(PM_IDLE):
|
|
{
|
|
/* Logic for PM_IDLE goes here */
|
|
|
|
}
|
|
break;
|
|
|
|
case(PM_STANDBY):
|
|
{
|
|
/* Logic for PM_STANDBY goes here */
|
|
|
|
}
|
|
break;
|
|
|
|
case(PM_SLEEP):
|
|
{
|
|
/* Logic for PM_SLEEP goes here */
|
|
|
|
}
|
|
break;
|
|
|
|
default:
|
|
/* Should not get here */
|
|
|
|
break;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: up_pm_prepare
|
|
*
|
|
* Description:
|
|
* Request the driver to prepare for a new power state. This is a warning
|
|
* that the system is about to enter into a new power state. The driver
|
|
* should begin whatever operations that may be required to enter power
|
|
* state. The driver may abort the state change mode by returning a
|
|
* non-zero value from the callback function.
|
|
*
|
|
* Input Parameters:
|
|
*
|
|
* cb - Returned to the driver. The driver version of the callback
|
|
* structure may include additional, driver-specific state data at
|
|
* the end of the structure.
|
|
*
|
|
* pmstate - Identifies the new PM state
|
|
*
|
|
* Returned Value:
|
|
* Zero - (OK) means the event was successfully processed and that the
|
|
* driver is prepared for the PM state change.
|
|
*
|
|
* Non-zero - means that the driver is not prepared to perform the tasks
|
|
* needed achieve this power setting and will cause the state
|
|
* change to be aborted. NOTE: The prepare() method will also
|
|
* be called when reverting from lower back to higher power
|
|
* consumption modes (say because another driver refused a
|
|
* lower power state change). Drivers are not permitted to
|
|
* return non-zero values when reverting back to higher power
|
|
* consumption modes!
|
|
*
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_PM
|
|
static int up_pm_prepare(struct pm_callback_s *cb, int domain,
|
|
enum pm_state_e pmstate)
|
|
{
|
|
/* Logic to prepare for a reduced power state goes here. */
|
|
|
|
return OK;
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Public Functions
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Name: s32k1xx_earlyserialinit
|
|
*
|
|
* Description:
|
|
* Performs the low level UART initialization early in debug so that the
|
|
* serial console will be available during bootup. This must be called
|
|
* before up_serialinit.
|
|
*
|
|
****************************************************************************/
|
|
|
|
void s32k1xx_earlyserialinit(void)
|
|
{
|
|
/* NOTE: This function assumes that low level hardware configuration
|
|
* -- including all clocking and pin configuration -- was performed by the
|
|
* function s32k1xx_lowsetup() earlier in the boot sequence.
|
|
*/
|
|
|
|
/* Enable the console UART. The other UARTs will be initialized if and
|
|
* when they are first opened.
|
|
*/
|
|
|
|
#ifdef CONSOLE_DEV
|
|
CONSOLE_DEV.isconsole = true;
|
|
s32k1xx_setup(&CONSOLE_DEV);
|
|
#endif
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: up_serialinit
|
|
*
|
|
* Description:
|
|
* Register serial console and serial ports. This assumes
|
|
* that s32k1xx_earlyserialinit was called previously.
|
|
*
|
|
****************************************************************************/
|
|
|
|
void up_serialinit(void)
|
|
{
|
|
#ifdef CONFIG_PM
|
|
int ret;
|
|
|
|
/* Register to receive power management callbacks */
|
|
|
|
ret = pm_register(&g_serial_pmcb);
|
|
DEBUGASSERT(ret == OK);
|
|
UNUSED(ret);
|
|
#endif
|
|
|
|
#ifdef CONSOLE_DEV
|
|
uart_register("/dev/console", &CONSOLE_DEV);
|
|
#endif
|
|
|
|
/* Register all UARTs */
|
|
|
|
uart_register("/dev/ttyS0", &TTYS0_DEV);
|
|
#ifdef TTYS1_DEV
|
|
uart_register("/dev/ttyS1", &TTYS1_DEV);
|
|
#endif
|
|
#ifdef TTYS2_DEV
|
|
uart_register("/dev/ttyS2", &TTYS2_DEV);
|
|
#endif
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: up_putc
|
|
*
|
|
* Description:
|
|
* Provide priority, low-level access to support OS debug writes
|
|
*
|
|
****************************************************************************/
|
|
|
|
int up_putc(int ch)
|
|
{
|
|
#ifdef CONSOLE_DEV
|
|
struct s32k1xx_uart_s *priv = (struct s32k1xx_uart_s *)CONSOLE_DEV.priv;
|
|
uint32_t ie;
|
|
|
|
s32k1xx_disableuartint(priv, &ie);
|
|
|
|
/* Check for LF */
|
|
|
|
if (ch == '\n')
|
|
{
|
|
/* Add CR */
|
|
|
|
s32k1xx_lowputc('\r');
|
|
}
|
|
|
|
s32k1xx_lowputc(ch);
|
|
s32k1xx_restoreuartint(priv, ie);
|
|
#endif
|
|
|
|
return ch;
|
|
}
|
|
|
|
#else /* USE_SERIALDRIVER */
|
|
|
|
/****************************************************************************
|
|
* Name: up_putc
|
|
*
|
|
* Description:
|
|
* Provide priority, low-level access to support OS debug writes
|
|
*
|
|
****************************************************************************/
|
|
|
|
int up_putc(int ch)
|
|
{
|
|
#if CONSOLE_LPUART > 0
|
|
/* Check for LF */
|
|
|
|
if (ch == '\n')
|
|
{
|
|
/* Add CR */
|
|
|
|
up_lowputc('\r');
|
|
}
|
|
|
|
up_lowputc(ch);
|
|
#endif
|
|
|
|
return ch;
|
|
}
|
|
|
|
#endif /* USE_SERIALDRIVER */
|