b0984fe674
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4459 42af7a65-404d-4744-a932-0658087f49c3
191 lines
9.9 KiB
C
191 lines
9.9 KiB
C
/************************************************************************************
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* arch/arm/src/lpc17xx/lpc17_qei.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H
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#define __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "lpc17_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register offsets *****************************************************************/
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/* Control registers */
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#define LPC17_QEI_CON_OFFSET 0x0000 /* Control register */
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#define LPC17_QEI_STAT_OFFSET 0x0004 /* Encoder status register */
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#define LPC17_QEI_CONF_OFFSET 0x0008 /* Configuration register */
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/* Position, index, and timer registers */
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#define LPC17_QEI_POS_OFFSET 0x000c /* Position register */
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#define LPC17_QEI_MAXPOS_OFFSET 0x0010 /* Maximum position register */
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#define LPC17_QEI_CMPOS0_OFFSET 0x0014 /* Position compare register */
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#define LPC17_QEI_CMPOS1_OFFSET 0x0018 /* Position compare register */
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#define LPC17_QEI_CMPOS2_OFFSET 0x001c /* Position compare register */
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#define LPC17_QEI_INXCNT_OFFSET 0x0020 /* Index count register */
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#define LPC17_QEI_INXCMP_OFFSET 0x0024 /* Index compare register */
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#define LPC17_QEI_LOAD_OFFSET 0x0028 /* Velocity timer reload register */
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#define LPC17_QEI_TIME_OFFSET 0x002c /* Velocity timer register */
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#define LPC17_QEI_VEL_OFFSET 0x0030 /* Velocity counter register */
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#define LPC17_QEI_CAP_OFFSET 0x0034 /* Velocity capture register */
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#define LPC17_QEI_VELCOMP_OFFSET 0x0038 /* Velocity compare register */
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#define LPC17_QEI_FILTER_OFFSET 0x003c /* Digital filter register */
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/* Interrupt registers */
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#define LPC17_QEI_IEC_OFFSET 0x0fd8 /* Interrupt enable clear register */
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#define LPC17_QEI_IES_OFFSET 0x0fdc /* Interrupt enable set register */
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#define LPC17_QEI_INTSTAT_OFFSET 0x0fe0 /* Interrupt status register */
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#define LPC17_QEI_IE_OFFSET 0x0fe4 /* Interrupt enable register */
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#define LPC17_QEI_CLR_OFFSET 0x0fe8 /* Interrupt status clear register */
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#define LPC17_QEI_SET_OFFSET 0x0fec /* Interrupt status set register */
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/* Register addresses ***************************************************************/
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/* Control registers */
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#define LPC17_QEI_CON (LPC17_QEI_BASE+LPC17_QEI_CON_OFFSET)
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#define LPC17_QEI_STAT (LPC17_QEI_BASE+LPC17_QEI_STAT_OFFSET)
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#define LPC17_QEI_CONF (LPC17_QEI_BASE+LPC17_QEI_CONF_OFFSET)
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/* Position, index, and timer registers */
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#define LPC17_QEI_POS (LPC17_QEI_BASE+LPC17_QEI_POS_OFFSET)
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#define LPC17_QEI_MAXPOS (LPC17_QEI_BASE+LPC17_QEI_MAXPOS_OFFSET)
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#define LPC17_QEI_CMPOS0 (LPC17_QEI_BASE+LPC17_QEI_CMPOS0_OFFSET)
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#define LPC17_QEI_CMPOS1 (LPC17_QEI_BASE+LPC17_QEI_CMPOS1_OFFSET)
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#define LPC17_QEI_CMPOS2 (LPC17_QEI_BASE+LPC17_QEI_CMPOS2_OFFSET)
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#define LPC17_QEI_INXCNT (LPC17_QEI_BASE+LPC17_QEI_INXCNT_OFFSET)
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#define LPC17_QEI_INXCMP (LPC17_QEI_BASE+LPC17_QEI_INXCMP_OFFSET)
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#define LPC17_QEI_LOAD (LPC17_QEI_BASE+LPC17_QEI_LOAD_OFFSET)
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#define LPC17_QEI_TIME (LPC17_QEI_BASE+LPC17_QEI_TIME_OFFSET)
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#define LPC17_QEI_VEL (LPC17_QEI_BASE+LPC17_QEI_VEL_OFFSET)
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#define LPC17_QEI_CAP (LPC17_QEI_BASE+LPC17_QEI_CAP_OFFSET)
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#define LPC17_QEI_VELCOMP (LPC17_QEI_BASE+LPC17_QEI_VELCOMP_OFFSET)
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#define LPC17_QEI_FILTER (LPC17_QEI_BASE+LPC17_QEI_FILTER_OFFSET)
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/* Interrupt registers */
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#define LPC17_QEI_IEC (LPC17_QEI_BASE+LPC17_QEI_IEC_OFFSET)
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#define LPC17_QEI_IES (LPC17_QEI_BASE+LPC17_QEI_IES_OFFSET)
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#define LPC17_QEI_INTSTAT (LPC17_QEI_BASE+LPC17_QEI_INTSTAT_OFFSET)
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#define LPC17_QEI_IE (LPC17_QEI_BASE+LPC17_QEI_IE_OFFSET)
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#define LPC17_QEI_CLR (LPC17_QEI_BASE+LPC17_QEI_CLR_OFFSET)
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#define LPC17_QEI_SET (LPC17_QEI_BASE+LPC17_QEI_SET_OFFSET)
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/* Register bit definitions *********************************************************/
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/* The following registers hold 32-bit integer values and have no bit fields defined
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* in this section:
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*
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* Position register (POS)
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* Maximum position register (MAXPOS)
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* Position compare register 0 (CMPOS0)
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* Position compare register 1 (CMPOS)
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* Position compare register 2 (CMPOS2)
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* Index count register (INXCNT)
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* Index compare register (INXCMP)
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* Velocity timer reload register (LOAD)
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* Velocity timer register (TIME)
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* Velocity counter register (VEL)
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* Velocity capture register (CAP)
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* Velocity compare register (VELCOMP)
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* Digital filter register (FILTER)
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*/
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/* Control registers */
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/* Control register */
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#define QEI_CON_RESP (1 << 0) /* Bit 0: Reset position counter */
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#define QEI_CON_RESPI (1 << 1) /* Bit 1: Reset position counter on index */
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#define QEI_CON_RESV (1 << 2) /* Bit 2: Reset velocity */
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#define QEI_CON_RESI (1 << 3) /* Bit 3: Reset index counter */
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/* Bits 4-31: reserved */
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/* Encoder status register */
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#define QEI_STAT_DIR (1 << 0) /* Bit 0: Direction bit */
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/* Bits 1-31: reserved */
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/* Configuration register */
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#define QEI_CONF_DIRINV (1 << 0) /* Bit 0: Direction invert */
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#define QEI_CONF_SIGMODE (1 << 1) /* Bit 1: Signal Mode */
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#define QEI_CONF_CAPMODE (1 << 2) /* Bit 2: Capture Mode */
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#define QEI_CONF_INVINX (1 << 3) /* Bit 3: Invert Index */
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/* Bits 4-31: reserved */
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/* Position, index, and timer registers (all 32-bit integer values with not bit fields */
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/* Interrupt registers */
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/* Interrupt enable clear register (IEC), Interrupt enable set register (IES),
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* Interrupt status register (INTSTAT), Interrupt enable register (IE), Interrupt
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* status clear register (CLR), and Interrupt status set register (SET) common
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* bit definitions.
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*/
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#define QEI_INT_INX (1 << 0) /* Bit 0: Index pulse detected */
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#define QEI_INT_TIM (1 << 1) /* Bit 1: Velocity timer overflow occurred */
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#define QEI_INT_VELC (1 << 2) /* Bit 2: Captured velocity less than compare velocity */
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#define QEI_INT_DIR (1 << 3) /* Bit 3: Change of direction detected */
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#define QEI_INT_ERR (1 << 4) /* Bit 4: Encoder phase error detected */
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#define QEI_INT_ENCLK (1 << 5) /* Bit 5: Eencoder clock pulse detected */
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#define QEI_INT_POS0 (1 << 6) /* Bit 6: Position 0 compare equal to current position */
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#define QEI_INT_POS1 (1 << 7) /* Bit 7: Position 1 compare equal to current position */
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#define QEI_INT_POS2 (1 << 8) /* Bit 8: Position 2 compare equal to current position */
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#define QEI_INT_REV (1 << 9) /* Bit 9: Index compare value equal to current index count */
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#define QEI_INT_POS0REV (1 << 10) /* Bit 10: Combined position 0 and revolution count interrupt */
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#define QEI_INT_POS1REV (1 << 11) /* Bit 11: Position 1 and revolution count interrupt */
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#define QEI_INT_POS2REV (1 << 12) /* Bit 12: Position 2 and revolution count interrupt */
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/* Bits 13-31: reserved */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_QEI_H */
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