3c05da536a
HPET can be used as system clock for x86_64 to set HPET as system clock you have to enable: CONFIG_ONESHOT=y CONFIG_ALARM_ARCH=y CONFIG_INTEL64_ONESHOT=y CONFIG_ARCH_INTEL64_HPET_ALARM=y Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
79 lines
2.5 KiB
Plaintext
79 lines
2.5 KiB
Plaintext
############################################################################
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# arch/x86_64/src/intel64/Make.defs
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#
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# Licensed to the Apache Software Foundation (ASF) under one or more
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# contributor license agreements. See the NOTICE file distributed with
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# this work for additional information regarding copyright ownership. The
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# ASF licenses this file to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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#
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############################################################################
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include common/Make.defs
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CMN_CSRCS += intel64_createstack.c intel64_initialstate.c intel64_irq.c
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CMN_CSRCS += intel64_map_region.c intel64_regdump.c intel64_releasestack.c
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CMN_CSRCS += intel64_rtc.c intel64_restore_auxstate.c intel64_savestate.c
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CMN_CSRCS += intel64_stackframe.c intel64_schedulesigaction.c
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CMN_CSRCS += intel64_sigdeliver.c intel64_usestack.c x86_64_tcbinfo.c
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CMN_CSRCS += intel64_systemreset.c intel64_freq.c intel64_cache.c
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# Required Intel64 files
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CHIP_ASRCS = intel64_saveusercontext.S intel64_fullcontextrestore.S intel64_vectors.S intel64_head.S
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CHIP_CSRCS = intel64_start.c intel64_handlers.c intel64_idle.c intel64_lowsetup.c
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CHIP_CSRCS += intel64_serial.c intel64_rng.c intel64_check_capability.c
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CHIP_CSRCS += intel64_cpu.c
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ifeq ($(CONFIG_MM_PGALLOC),y)
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CHIP_CSRCS += intel64_pgalloc.c
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endif
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ifeq ($(CONFIG_ARCH_HAVE_TESTSET), y)
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CHIP_ASRCS += intel64_testset.S
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endif
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ifeq ($(CONFIG_SMP),y)
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CHIP_CSRCS += intel64_cpuidlestack.c
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CHIP_CSRCS += intel64_cpupause.c
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CHIP_CSRCS += intel64_cpustart.c
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endif
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# Configuration-dependent intel64 files
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ifeq ($(CONFIG_MULTBOOT2_FB_TERM),y)
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CHIP_CSRCS += intel64_mbfb.c
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endif
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ifeq ($(CONFIG_ARCH_INTEL64_HAVE_TSC),y)
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ifeq ($(CONFIG_SCHED_TICKLESS),y)
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CHIP_CSRCS += intel64_tsc_tickless.c
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else
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CHIP_CSRCS += intel64_tsc_timerisr.c
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endif
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endif
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ifeq ($(CONFIG_INTEL64_HPET),y)
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CHIP_CSRCS += intel64_hpet.c
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endif
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ifeq ($(CONFIG_ARCH_INTEL64_HPET_ALARM),y)
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CHIP_CSRCS += intel64_hpet_alarm.c
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endif
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ifeq ($(CONFIG_INTEL64_ONESHOT),y)
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CHIP_CSRCS += intel64_oneshot.c intel64_oneshot_lower.c
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endif
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ifeq ($(CONFIG_ARCH_FPU),y)
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CHIP_CSRCS += intel64_fpucmp.c
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endif |