c7f9d9b150
since it's fixed by: https://github.com/apache/incubator-nuttx/pull/6909 Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
165 lines
8.5 KiB
Plaintext
165 lines
8.5 KiB
Plaintext
P112 README
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===========
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The P112 is notable because it was the first of the hobbyist single board
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computers to reach the production stage. The P112 hobbyist computers
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were relatively widespread and inspired other hobbyist centered home brew
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computing projects such as N8VEM home brew computing project. The P112
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project still maintains many devoted enthusiasts and has an online
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repository of software and other information.
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The P112 computer originated as a commercial product of "D-X Designs Pty
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Ltd" of Australia. They describe the computer as "The P112 is a stand-alone
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8-bit CPU board. Typically running CP/M (tm) or a similar operating system,
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it provides a Z80182 (Z-80 upgrade) CPU with up to 1MB of memory, serial,
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parallel and diskette IO, and realtime clock, in a 3.5-inch drive form factor.
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Powered solely from 5V, it draws 150mA (nominal: not including disk drives)
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with a 16MHz CPU clock. Clock speeds up to 24.576MHz are possible."
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The P112 board was last available new in 1996 by Dave Brooks. In late 2004
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on the Usenet Newsgroup comp.os.cpm, talk about making another run of P112
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boards was discussed. David Griffith decided to produce additional P112 kits
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with Dave Brooks blessing and the assistance of others. In addition Terry
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Gulczynski makes additional P112 derivative hobbyist home brew computers.
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Hal Bower was very active in the mid 1990's on the P112 project and ported
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the "Banked/Portable BIOS".
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Dave Griffith was successfully funded through Kickstarter for another run
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of P112 boards in November of 2012.
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Pin Configuration
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=================
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The P112 is based on the 5V Z8018216FSG running at 16MHz. The Z8018216FSG
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comes in a 100-pin QFP package:
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PIN NAME
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1 /INT0 INT0, pulled up, J1 DIN48 pin 13C
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2 /INT1/PC6 FINTR, Floppy disk controller
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3 /INT2/PC7 PINTR1, Floppy disk controller
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4 ST ST, to AEN of Floppy disk controller
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5 A0 A0-A12 Common memory bus
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...
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17 A12 " "
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18 VSS ---
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19 A13 A13-A17 Common memory bus
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...
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23 A17 " "
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24 A18/TOUT A18 Common memory bus
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25 VDD ---
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26 A19 A19 Common memory bus
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27 D0 D0-D4 Common memory bus
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...
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30 D3 " "
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31 D4 D4-D7 Common memory bus
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...
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34 D7 " "
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35 /RTS0/PB0 RTS0, 20-pin P14, pin 3
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36 /CTS0/PB1 CTS0, pulled high (U16), 20-pin P14, pin 4
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37 /DCD0/PB2 DCD0, pulled high (U16), 20-pin P14, pin 10
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38 TXA0/PB3 TXA0, 20-pin P14, pin 8
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39 RXA0/PB4 RXA0, pulled high (U17), 20-pin P14, pin 2
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40 TXA1/PB5 TXA1, 20-pin P14, pin 1
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41 RXA1/PB6 RXA1, pulled high (U17), 20-pin P14, pin 9
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42 RXS//CTS1/PB7 CTS1, pulled high (U17), 20-pin P14, pin 7
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43 CKA0//DREQ0 /DREQ0, DMA Request Select, 5-pin P2, pin 2
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44 VSS ---
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45 CKA1//TEND0 /TEND0, J1 DIN48 pin 14A
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46 TXS//DTR//REQB//HINTR DTRB, 20-pin P14, pin 6
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47 CKS//W//REQB//HTXRDY SIORQ, DMA Request Select, 5-pin P2, pin 5 (may be DREQ 0 or DREQ1)
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48 /DREQ1 /DREQ1, DMA Request Select, 5-pin P2, pin 4
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49 VDD ---
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50 /TEND1//RTSB//HRXRDY NB /TEND1 = RTSB, 20-pin P14, pin 5; J1 DIN48 pin 14B
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51 /RAMCS /RAMCS, Chip select logic (U11B); also J1 DIN48 pin 9B
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52 /ROMCS /ROMCS, Chip select logic (P2); also J1 DIN48 pin 12B
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53 EV1 Grounded
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54 EV2 Grounded
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55 PA0/HD0 IO, U6 DS1202 Serial Timekeeping chip
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56 PA1/HD1 CLK, U6 DS1202 Serial Timekeeping chip
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57 PA2/HD2 /RST, U6 DS1202 Serial Timekeeping chip
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58 PA3/HD3 N/C
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59 PA4/HD4 N/C
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60 PA5/HD5 U12 NMF0512S, Isolated 1W regulated single output DC/DC converter
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61 PA6/HD6 DSR, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
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62 PA7/HD7 RTS, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
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63 /W//REQA/PC5 WREQA, N/C
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64 /DTR//REQA/PC3 DTRA, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
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65 /MWR/PC2//RTSA /MWR, Common memory bus signal
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66 /CTSA/PC1 CTSA, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
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67 /DCDA/PC0 DCDA, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
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68 /SYNCA/PC4 SYNCA, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
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69 /RTXCA ?
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70 VSS ---
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71 /IOCS/IEO /IOCS, Logic circuit with M1, generates LIVE which conditions inputs
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to the floppy disk controller
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72 IEI IEI, J1 DIN48 pin 14C
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73 VDD ---
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74 RXDA RXDA, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
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75 /TRXCA ?
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76 TXDA TXDA, U7 LT1133, Advanced Low Power 5V RS232 Driver/Receiver
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77 /DCDB//HRD DCDB, pulled high (U16), 20-pin P14, pin 12
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78 /CTSB//HWR DCDB, pulled high (U17), 20-pin P14, pin 11
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79 TXDB//HDDIS TXDB, 20-pin P14, pin 14
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80 /TRXCB/HA0 TRXCB, pulled high (U17), 20-pin P14, pin 15
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81 RXDB/HA1 RXDB, pulled high (U16), 20-pin P14, pin 16
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82 /RTXCB/HA2 RTXCB, pulled high (U17), 20-pin P14, pin 17
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83 /SYNCB//HCS SYNCB, pulled high (U16), 20-pin P14, pin 18
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84 /HALT ?
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85 /RFSH ?
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86 /IORQ /IORQ, J1 DIN48 pin 12A
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87 /MRD//MREQ /MRD, Common memory bus signal
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88 E E, Conditions inputs to floppy disk controller; also J1 DIN48 pin 13B
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89 /M1 /M1, Logic circuit with /IOCS, generates LIVE which conditions inputs
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to the floppy disk controller; also J1 DIN48 pin 11A
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90 /WR /WR, Common memory bus; Conditions inputs to floppy disk controller;
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also J1 DIN48 pin 12C
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91 /RD /RD, J1 DIN48 pin 11C
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92 PHI PHI, J1 DIN48 pin 15B
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93 VSS ---
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94 XTAL 16 MHz XTAL
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95 EXTAL 16 MHz XTAL
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96 /WAIT /WAIT, J1 DIN48 pin 11B
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97 /BUSACK ?
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98 /BUSREQ /BUSREQ, Pulled high
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99 /RESET /RST (to lots of places)
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100 /NMI /NMI, Pulled high
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P112 Serial Console
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===================
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The UARTs are not used on the P112 board (the UART signals are available
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off-board through P14). The serial console is provided by U7 LT1133,
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Advanced Low Power 5V RS232 Driver/Receiver that connects to the P112 via
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the Z85230 ESCC channel A.
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Status
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======
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2020-4-11: Support for CONFIG_CAN_PASS_STRUCTS was removed in NuttX-9.1.
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This was necessary to enforce some POSIX interface compliance but also
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means that ALL older SDCC versions will no long build with NuttX. I have
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been told that the newest SDCC compilers can indeed pass structure and
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union parameters and return values. If that is correct, then perhaps
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the newer SDCC compilers will be used. Otherwise, it will be necessary
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to use some other, more compliant compiler.
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2014-8-22: After some time idling away, I tried rebuilding with Windows 8,
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the latest MinGW and the latest SDCC. I fixed a few things but there a
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still a few issues. The last "show stopper" before I gave up for now was
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during building dependencies:
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ASlink-Error-<cannot open> : "bin/mm_initialize.rel"
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Clearly there is something wrong with the command line options given to
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SDCC because it is trying to compile and link when we really only want
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dependencies. I did not spend very much time trying to solve the problem;
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I assume that it is not too difficult.
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2014-9-15: There has been a lot of change to the address environment APIs
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with the integration of address environments on the Cortex-A. It is
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likely that there is some breakage due to incompatibilities with the
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Z180's mini-MMU.
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