Dave Marples d0cda60442 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

..

chip.h

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

irq.h

Rename CONFIG_STM32_STM32F40XX to CONFIG_STM32_STM32FXXXX since it is used by F4 parts other than F40x

2017-07-06 10:20:14 -06:00

stm32f10xxx_irq.h

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stm32f20xxx_irq.h

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stm32f30xxx_irq.h

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stm32f33xxx_irq.h

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stm32f37xxx_irq.h

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stm32f40xxx_irq.h

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stm32l15xxx_irq.h

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