377 lines
12 KiB
C
377 lines
12 KiB
C
/****************************************************************************
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* arch/risc-v/include/csr.h
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*
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* Copyright (C) 2016 Ken Pettit. All rights reserved.
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* Author: Ken Pettit <pettitkd@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_RISCV_INCLUDE_CSR_H
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#define __ARCH_RISCV_INCLUDE_CSR_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* User Trap Registers */
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#define CSR_USTATUS 0x000
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#define CSR_UIE 0x004
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#define CSR_UTVEC 0x005
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/* User Trap Handling Registers */
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#define CSR_USCRATCH 0x040
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#define CSR_UEPC 0x041
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#define CSR_UCAUSE 0x042
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#define CSR_UTVAL 0x043
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#define CSR_UIP 0x044
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/* User Floating-Point Registers */
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#define CSR_FFLAGS 0x001
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#define CSR_FRM 0x002
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#define CSR_FCSR 0x003
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/* User Counter/Times Registers */
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#define CSR_CYCLE 0xC00
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#define CSR_TIME 0xC01
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#define CSR_INSTRET 0xC02
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#define CSR_HPCOUNTER3 0xC03
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#define CSR_HPCOUNTER4 0xC04
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#define CSR_HPCOUNTER5 0xC05
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#define CSR_HPCOUNTER6 0xC06
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#define CSR_HPCOUNTER7 0xC07
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#define CSR_HPCOUNTER8 0xC08
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#define CSR_HPCOUNTER9 0xC09
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#define CSR_HPCOUNTER10 0xC0A
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#define CSR_HPCOUNTER11 0xC0B
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#define CSR_HPCOUNTER12 0xC0C
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#define CSR_HPCOUNTER13 0xC0D
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#define CSR_HPCOUNTER14 0xC0E
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#define CSR_HPCOUNTER15 0xC0F
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#define CSR_HPCOUNTER16 0xC10
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#define CSR_HPCOUNTER17 0xC11
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#define CSR_HPCOUNTER18 0xC12
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#define CSR_HPCOUNTER19 0xC13
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#define CSR_HPCOUNTER20 0xC14
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#define CSR_HPCOUNTER21 0xC15
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#define CSR_HPCOUNTER22 0xC16
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#define CSR_HPCOUNTER24 0xC17
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#define CSR_HPCOUNTER25 0xC18
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#define CSR_HPCOUNTER26 0xC19
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#define CSR_HPCOUNTER27 0xC1A
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#define CSR_HPCOUNTER28 0xC1B
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#define CSR_HPCOUNTER29 0xC1C
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#define CSR_HPCOUNTER30 0xC1D
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#define CSR_HPCOUNTER31 0xC1F
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#define CSR_CYCLEH 0xC80
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#define CSR_TIMEH 0xC81
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#define CSR_INSTRETH 0xC82
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#define CSR_HPCOUNTER3H 0xC83
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#define CSR_HPCOUNTER4H 0xC84
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#define CSR_HPCOUNTER5H 0xC85
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#define CSR_HPCOUNTER6H 0xC86
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#define CSR_HPCOUNTER7H 0xC87
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#define CSR_HPCOUNTER8H 0xC88
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#define CSR_HPCOUNTER9H 0xC89
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#define CSR_HPCOUNTER10H 0xC8A
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#define CSR_HPCOUNTER11H 0xC8B
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#define CSR_HPCOUNTER12H 0xC8C
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#define CSR_HPCOUNTER13H 0xC8D
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#define CSR_HPCOUNTER14H 0xC8E
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#define CSR_HPCOUNTER15H 0xC8F
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#define CSR_HPCOUNTER16H 0xC90
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#define CSR_HPCOUNTER17H 0xC91
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#define CSR_HPCOUNTER18H 0xC92
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#define CSR_HPCOUNTER19H 0xC93
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#define CSR_HPCOUNTER20H 0xC94
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#define CSR_HPCOUNTER21H 0xC95
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#define CSR_HPCOUNTER22H 0xC96
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#define CSR_HPCOUNTER24H 0xC97
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#define CSR_HPCOUNTER25H 0xC98
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#define CSR_HPCOUNTER26H 0xC99
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#define CSR_HPCOUNTER27H 0xC9A
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#define CSR_HPCOUNTER28H 0xC9B
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#define CSR_HPCOUNTER29H 0xC9C
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#define CSR_HPCOUNTER30H 0xC9D
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#define CSR_HPCOUNTER31H 0xC9F
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/* Supervisor Trap Setup Registers */
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#define CSR_SSTATUS 0x100
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#define CSR_SEDELEG 0x102
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#define CSR_SIDELEG 0x103
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#define CSR_SIE 0x104
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#define CSR_STVEC 0x105
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#define CSR_SCOUNTEREN 0x106
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/* Supervisor Trap Handling Registers */
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#define CSR_SSCRATCH 0x140
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#define CSR_SEPC 0x141
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#define CSR_SCAUSE 0x142
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#define CSR_STVAL 0x143
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#define CSR_SIP 0x144
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/* Supervisor Protection and Translation Registers */
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#define CSR_SATP 0x180
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/* Machine Information Registers */
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#define CSR_MVENDORID 0xF11
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#define CSR_MARCHID 0xF12
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#define CSR_MIMPID 0xF13
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#define CSR_MHARTID 0xF14
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/* Machine Trap Registers */
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MEDELEG 0x302
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#define CSR_MIDELEG 0x303
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MCOUNTEREN 0x306
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/* Machine Trap Handling */
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#define CSR_MSCRATCH 0x340
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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#define CSR_MTVAL 0x343
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#define CSR_MIP 0x344
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/* Machine Protection and Translation */
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#define CSR_PMPCFG0 0x3A0
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#define CSR_PMPCFG1 0x3A1
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#define CSR_PMPCFG2 0x3A2
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#define CSR_PMPCFG3 0x3A3
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#define CSR_PMPADDR0 0x3B0
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#define CSR_PMPADDR1 0x3B1
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#define CSR_PMPADDR2 0x3B2
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#define CSR_PMPADDR3 0x3B3
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#define CSR_PMPADDR4 0x3B4
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#define CSR_PMPADDR5 0x3B5
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#define CSR_PMPADDR6 0x3B6
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#define CSR_PMPADDR7 0x3B7
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#define CSR_PMPADDR8 0x3B8
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#define CSR_PMPADDR9 0x3B9
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#define CSR_PMPADDR10 0x3BA
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#define CSR_PMPADDR11 0x3BB
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#define CSR_PMPADDR12 0x3BC
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#define CSR_PMPADDR13 0x3BD
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#define CSR_PMPADDR14 0x3BE
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#define CSR_PMPADDR15 0x3BF
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/* Machine Timers and Counters */
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#define CSR_MCYCLE 0xB00
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#define CSR_MINSTRET 0xB02
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#define CSR_MHPMCOUNTER3 0xB03
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#define CSR_MHPMCOUNTER4 0xB04
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#define CSR_MHPMCOUNTER5 0xB05
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#define CSR_MHPMCOUNTER6 0xB06
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#define CSR_MHPMCOUNTER7 0xB07
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#define CSR_MHPMCOUNTER8 0xB08
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#define CSR_MHPMCOUNTER9 0xB09
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#define CSR_MHPMCOUNTER10 0xB0A
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#define CSR_MHPMCOUNTER11 0xB0B
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#define CSR_MHPMCOUNTER12 0xB0C
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#define CSR_MHPMCOUNTER13 0xB0D
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#define CSR_MHPMCOUNTER14 0xB0E
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#define CSR_MHPMCOUNTER15 0xB0F
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#define CSR_MHPMCOUNTER16 0xB10
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#define CSR_MHPMCOUNTER17 0xB11
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#define CSR_MHPMCOUNTER18 0xB12
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#define CSR_MHPMCOUNTER19 0xB13
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#define CSR_MHPMCOUNTER20 0xB14
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#define CSR_MHPMCOUNTER21 0xB15
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#define CSR_MHPMCOUNTER22 0xB16
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#define CSR_MHPMCOUNTER23 0xB17
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#define CSR_MHPMCOUNTER24 0xB18
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#define CSR_MHPMCOUNTER25 0xB19
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#define CSR_MHPMCOUNTER26 0xB1A
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#define CSR_MHPMCOUNTER27 0xB1B
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#define CSR_MHPMCOUNTER28 0xB1C
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#define CSR_MHPMCOUNTER29 0xB1D
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#define CSR_MHPMCOUNTER30 0xB1E
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#define CSR_MHPMCOUNTER31 0xB1F
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#define CSR_MCYCLEH 0xB80
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#define CSR_MINSTRETH 0xB82
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#define CSR_MHPMCOUNTER3H 0xB83
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#define CSR_MHPMCOUNTER4H 0xB84
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#define CSR_MHPMCOUNTER5H 0xB85
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#define CSR_MHPMCOUNTER6H 0xB86
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#define CSR_MHPMCOUNTER7H 0xB87
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#define CSR_MHPMCOUNTER8H 0xB88
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#define CSR_MHPMCOUNTER9H 0xB89
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#define CSR_MHPMCOUNTER10H 0xB8A
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#define CSR_MHPMCOUNTER11H 0xB8B
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#define CSR_MHPMCOUNTER12H 0xB8C
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#define CSR_MHPMCOUNTER13H 0xB8D
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#define CSR_MHPMCOUNTER14H 0xB8E
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#define CSR_MHPMCOUNTER15H 0xB8F
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#define CSR_MHPMCOUNTER16H 0xB90
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#define CSR_MHPMCOUNTER17H 0xB91
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#define CSR_MHPMCOUNTER18H 0xB92
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#define CSR_MHPMCOUNTER19H 0xB93
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#define CSR_MHPMCOUNTER20H 0xB94
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#define CSR_MHPMCOUNTER21H 0xB95
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#define CSR_MHPMCOUNTER22H 0xB96
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#define CSR_MHPMCOUNTER23H 0xB97
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#define CSR_MHPMCOUNTER24H 0xB98
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#define CSR_MHPMCOUNTER25H 0xB99
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#define CSR_MHPMCOUNTER26H 0xB9A
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#define CSR_MHPMCOUNTER27H 0xB9B
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#define CSR_MHPMCOUNTER28H 0xB9C
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#define CSR_MHPMCOUNTER29H 0xB9D
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#define CSR_MHPMCOUNTER30H 0xB9E
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#define CSR_MHPMCOUNTER31H 0xB9F
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/* Machine Counter Setup */
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#define CSR_MPHEVENT3 0x323
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#define CSR_MPHEVENT4 0x324
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#define CSR_MPHEVENT5 0x325
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#define CSR_MPHEVENT6 0x326
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#define CSR_MPHEVENT7 0x327
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#define CSR_MPHEVENT8 0x328
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#define CSR_MPHEVENT9 0x329
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#define CSR_MPHEVENT10 0x32A
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#define CSR_MPHEVENT11 0x32B
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#define CSR_MPHEVENT12 0x32C
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#define CSR_MPHEVENT13 0x32D
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#define CSR_MPHEVENT14 0x32E
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#define CSR_MPHEVENT15 0x32F
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#define CSR_MPHEVENT16 0x330
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#define CSR_MPHEVENT17 0x331
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#define CSR_MPHEVENT18 0x332
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#define CSR_MPHEVENT19 0x333
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#define CSR_MPHEVENT20 0x334
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#define CSR_MPHEVENT21 0x335
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#define CSR_MPHEVENT22 0x336
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#define CSR_MPHEVENT23 0x337
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#define CSR_MPHEVENT24 0x338
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#define CSR_MPHEVENT25 0x339
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#define CSR_MPHEVENT26 0x33A
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#define CSR_MPHEVENT27 0x33B
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#define CSR_MPHEVENT28 0x33C
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#define CSR_MPHEVENT29 0x33D
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#define CSR_MPHEVENT30 0x33E
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#define CSR_MPHEVENT31 0x33F
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/* Debug/Trace Registers */
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#define CSR_TSELECT 0x7A0
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#define CSR_TDATA1 0x7A1
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#define CSR_TDATA2 0x7A2
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#define CSR_TDATA3 0x7A3
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/* Debug interface CSRs */
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#define CSR_DCSR 0x7B0
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#define CSR_DPC 0x7B1
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#define CSR_DSCRATCH 0x7B2
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/* In mstatus register */
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#define MSTATUS_MIE (0x1 << 3) /* Machine Interrupt Enable */
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#define MSTATUS_MPIE (0x1 << 7) /* Machine Previous Interrupt Enable */
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#define MSTATUS_MPPM (0x3 << 11) /* Machine Previous Privilege (m-mode) */
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#define MSTATUS_FS (0x3 << 13) /* Machine Floating-point Status */
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#define MSTATUS_FS_INIT (0x1 << 13)
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#define MSTATUS_FS_CLEAN (0x2 << 13)
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#define MSTATUS_FS_DIRTY (0x3 << 13)
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/* In mie (machine interrupt enable) register */
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#define MIE_MSIE (0x1 << 3) /* Machine Software Interrupt Enable */
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#define MIE_MTIE (0x1 << 7) /* Machine Timer Interrupt Enable */
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#define MIE_MEIE (0x1 << 11) /* Machine External Interrupt Enable */
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/* In mip (machine interrupt pending) register */
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#define MIP_MTIP (0x1 << 7)
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#define CSR_STR(csr) #csr
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#define READ_CSR(reg) \
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({ \
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unsigned long tmp; \
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asm volatile("csrr %0, " CSR_STR(reg) : "=r"(tmp)); \
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tmp; \
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})
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#define WRITE_CSR(reg, val) \
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({ \
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asm volatile("csrw " CSR_STR(reg) ", %0" :: "rK"(val)); \
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})
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#define SET_CSR(reg, bits) \
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({ \
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asm volatile("csrs " CSR_STR(reg) ", %0" :: "rK"(bits)); \
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})
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#define CLEAR_CSR(reg, bits) \
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({ \
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asm volatile("csrc " CSR_STR(reg) ", %0" :: "rK"(bits)); \
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})
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/* In pmpcfg (PMP configuration) register */
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#define PMPCFG_R (1 << 0) /* readable ? */
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#define PMPCFG_W (1 << 1) /* writeable ? */
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#define PMPCFG_X (1 << 2) /* excutable ? */
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#define PMPCFG_A_OFF (0 << 3) /* null region (disabled) */
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#define PMPCFG_A_TOR (1 << 3) /* top of range */
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#define PMPCFG_A_NA4 (2 << 3) /* naturally aligned four-byte region */
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#define PMPCFG_A_NAPOT (3 << 3) /* naturally aligned power-of-two region */
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#define PMPCFG_A_MASK (3 << 3) /* address-matching mode mask */
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#define PMPCFG_L (1 << 7) /* locked ? */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_RISCV_INCLUDE_CSR_H */
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