3e76370919
Gregory Nutt has submitted the SGA and we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
621 lines
20 KiB
C
621 lines
20 KiB
C
/****************************************************************************
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* arch/avr/include/at32uc3/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_AVR_INCLUDE_AT32UC3_IRQ_H
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#define __ARCH_AVR_INCLUDE_AT32UC3_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* Configuration CONFIG_AVR32_GPIOIRQ must be selected to enable the overall
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* GPIO IRQ feature and CONFIG_AVR32_GPIOIRQSETA and/or
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* CONFIG_AVR32_GPIOIRQSETB must be enabled to select GPIOs to support
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* interrupts on.
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*/
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#ifndef CONFIG_AVR32_GPIOIRQ
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# undef CONFIG_AVR32_GPIOIRQSETA
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# undef CONFIG_AVR32_GPIOIRQSETB
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#endif
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/* IRQ numbers **************************************************************/
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/* Events. These exclude:
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*
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* - The Reset event which vectors directly either to 0x8000:0000 (uc3a) or
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* to 0xa000:0000 (uc3b).
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* - The OCD stop from the OSD system
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* - Autovectored interrupt requests
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*
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* Others vector relative to the contents of the EVBA register.
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*/
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#define AVR32_IRQ_UNREC 0 /* EVBA+0x00 Unrecoverable exception */
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#define AVR32_IRQ_TLBMULT 1 /* EVBA+0x04 TLB multiple hit */
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#define AVR32_IRQ_BUSDATA 2 /* EVBA+0x08 Bus error data fetch */
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#define AVR32_IRQ_BUSINST 3 /* EVBA+0x0c Bus error instruction fetch */
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#define AVR32_IRQ_NMI 4 /* EVBA+0x10 NMI */
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#define AVR32_IRQ_INSTADDR 5 /* EVBA+0x14 Instruction Address */
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#define AVR32_IRQ_ITLBPROT 6 /* EVBA+0x18 ITLB Protection */
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#define AVR32_IRQ_BP 7 /* EVBA+0x1c Breakpoint */
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#define AVR32_IRQ_INVINST 8 /* EVBA+0x20 Illegal Opcode */
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#define AVR32_IRQ_UNIMPINST 9 /* EVBA+0x24 Unimplemented instruction */
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#define AVR32_IRQ_PRIV 10 /* EVBA+0x28 Privilege violation */
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#define AVR32_IRQ_FP 11 /* EVBA+0x2c Floating-point */
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#define AVR32_IRQ_COP 12 /* EVBA+0x30 Coprocessor absent */
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#define AVR32_IRQ_RDDATA 13 /* EVBA+0x34 Data Address (Read) */
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#define AVR32_IRQ_WRDATA 14 /* EVBA+0x38 Data Address (Write) */
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#define AVR32_IRQ_RDDTLBPROT 15 /* EVBA+0x3c DTLB Protection (Read) */
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#define AVR32_IRQ_WRDTLBPROT 16 /* EVBA+0x40 DTLB Protection (Write) */
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#define AVR32_IRQ_DLTBMOD 17 /* EVBA+0x44 DTLB Modified */
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#define AVR32_IRQ_ITLBMISS 18 /* EVBA+0x50 ITLB Miss */
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#define AVR32_IRQ_RDDTLB 19 /* EVBA+0x60 DTLB Miss (Read) */
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#define AVR32_IRQ_WRDTLB 20 /* EVBA+0x70 DTLB Miss (Write) */
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#define AVR32_IRQ_SUPER 21 /* EVBA+0x100 Supervisor call */
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#define AVR32_IRQ_NEVENTS 22
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/* "The INTC collects interrupt requests from the peripherals, prioritizes
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* them, and delivers an interrupt request and an autovector to the CPU. The
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* AVR32 architecture supports 4 priority levels for regular, maskable
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* interrupts, and a Non-Maskable Interrupt (NMI)."
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*
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* "The INTC supports up to 64 groups of interrupts. Each group can have up
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* to 32 interrupt request lines, these lines are connected to the peripherals.
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* Each group has an Interrupt Priority Register (IPR) and an Interrupt Request
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* Register (IRR). The IPRs are used to assign a priority level and an autovector
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* to each group, and the IRRs are used to identify the active interrupt request
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* within each group. If a group has only one interrupt request line, an active
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* interrupt group uniquely identifies the active interrupt request line, and
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* the corresponding IRR is not needed. The INTC also provides one Interrupt
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* Cause Register (ICR) per priority level. These registers identify the group
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* that has a pending interrupt of the corresponding priority level. If several
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* groups have a pending interrupt of the same level, the group with the lowest
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* number takes priority."
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*/
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/* Only 19 groups (0-18) are used with the AT32UC3A/B: */
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#define AVR32_IRQ_INTPRIOS 4 /* 4 interrupt priorities */
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#define AVR32_IRQ_MAXGROUPS 64 /* Architecture supports up to 64 groups */
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#define AVR32_IRQ_NGROUPS 19 /* UC3 A/B support only 19 */
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/* Group 0 */
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#define AVR32_IRQ_BASEIRQGRP0 22
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#define AVR32_IRQ_NREQGRP0 1
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#define AVR32_IRQ_UC 22 /* 0 AVR32 UC CPU */
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/* Group 1 */
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#define AVR32_IRQ_BASEIRQGRP1 23
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#define AVR32_IRQ_NREQGRP1 10
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#define AVR32_IRQ_EIC0 23 /* 0 External Interrupt Controller 0 */
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#define AVR32_IRQ_EIC1 24 /* 1 External Interrupt Controller 1 */
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#define AVR32_IRQ_EIC2 25 /* 2 External Interrupt Controller 2 */
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#define AVR32_IRQ_EIC3 26 /* 3 External Interrupt Controller 3 */
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#define AVR32_IRQ_EIC4 27 /* 4 External Interrupt Controller 4 */
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#define AVR32_IRQ_EIC5 28 /* 5 External Interrupt Controller 5 */
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#define AVR32_IRQ_EIC6 29 /* 6 External Interrupt Controller 6 */
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#define AVR32_IRQ_EIC7 30 /* 7 External Interrupt Controller 7 */
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#define AVR32_IRQ_RTC 31 /* 8 Real Time Counter RTC */
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#define AVR32_IRQ_PM 32 /* 9 Power Manager PM */
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/* Group 2 */
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#define AVR32_IRQ_BASEIRQGRP2 33
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#define AVR32_IRQ_NREQGRP2 6
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#define AVR32_IRQ_GPIO0 33 /* 0 General Purpose Input/Output Controller 0 */
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#define AVR32_IRQ_GPIO1 34 /* 1 General Purpose Input/Output Controller 1 */
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#define AVR32_IRQ_GPIO2 35 /* 2 General Purpose Input/Output Controller 2 */
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#define AVR32_IRQ_GPIO3 36 /* 3 General Purpose Input/Output Controller 3 */
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#define AVR32_IRQ_GPIO4 37 /* 4 General Purpose Input/Output Controller 4 */
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#define AVR32_IRQ_GPIO5 38 /* 5 General Purpose Input/Output Controller 5 */
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/* Group 3 */
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#define AVR32_IRQ_BASEIRQGRP3 39
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#define AVR32_IRQ_NREQGRP3 7
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#define AVR32_IRQ_PDCA0 39 /* 0 Peripheral DMA Controller 0 */
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#define AVR32_IRQ_PDCA1 40 /* 1 Peripheral DMA Controller 1 */
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#define AVR32_IRQ_PDCA2 41 /* 2 Peripheral DMA Controller 2 */
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#define AVR32_IRQ_PDCA3 42 /* 3 Peripheral DMA Controller 3 */
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#define AVR32_IRQ_PDCA4 43 /* 4 Peripheral DMA Controller 4 */
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#define AVR32_IRQ_PDCA5 44 /* 5 Peripheral DMA Controller 5 */
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#define AVR32_IRQ_PDCA6 45 /* 6 Peripheral DMA Controller 6 */
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/* Group 4 */
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#define AVR32_IRQ_BASEIRQGRP4 46
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#define AVR32_IRQ_NREQGRP4 1
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#define AVR32_IRQ_FLASHC 46 /* 0 Flash Controller */
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/* Group 5 */
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#define AVR32_IRQ_BASEIRQGRP5 47
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#define AVR32_IRQ_NREQGRP5 1
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#define AVR32_IRQ_USART0 47 /* 0 Universal Synchronous/Asynchronous
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* Receiver/Transmitter 0 */
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/* Group 6 */
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#define AVR32_IRQ_BASEIRQGRP6 48
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#define AVR32_IRQ_NREQGRP6 1
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#define AVR32_IRQ_USART1 48 /* 0 Universal Synchronous/Asynchronous
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* Receiver/Transmitter 1 */
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/* Group 7 */
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#define AVR32_IRQ_BASEIRQGRP7 49
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#define AVR32_IRQ_NREQGRP7 1
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#define AVR32_IRQ_USART2 49 /* 0 Universal Synchronous/Asynchronous
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* Receiver/Transmitter 2 */
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#define AVR32_IRQ_BASEIRQGRP8 50
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#define AVR32_IRQ_NREQGRP8 0
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/* Group 9 */
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#define AVR32_IRQ_BASEIRQGRP9 50
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#define AVR32_IRQ_NREQGRP9 1
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#define AVR32_IRQ_SPI 50 /* 0 Serial Peripheral Interface */
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#define AVR32_IRQ_BASEIRQGRP10 51
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#define AVR32_IRQ_NREQGRP10 0
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/* Group 11 */
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#define AVR32_IRQ_BASEIRQGRP11 51
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#define AVR32_IRQ_NREQGRP11 1
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#define AVR32_IRQ_TWI 51 /* 0 Two-wire Interface TWI */
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/* Group 12 */
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#define AVR32_IRQ_BASEIRQGRP12 52
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#define AVR32_IRQ_NREQGRP12 1
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#define AVR32_IRQ_PWM 52 /* 0 Pulse Width Modulation Controller */
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/* Group 13 */
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#define AVR32_IRQ_BASEIRQGRP13 53
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#define AVR32_IRQ_NREQGRP13 1
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#define AVR32_IRQ_SSC 53 /* 0 Synchronous Serial Controller */
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/* Group 14 */
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#define AVR32_IRQ_BASEIRQGRP14 54
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#define AVR32_IRQ_NREQGRP14 3
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#define AVR32_IRQ_TC0 54 /* 0 Timer/Counter 0 */
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#define AVR32_IRQ_TC1 55 /* 1 Timer/Counter 1 */
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#define AVR32_IRQ_TC2 56 /* 2 Timer/Counter 2 */
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/* Group 15 */
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#define AVR32_IRQ_BASEIRQGRP15 57
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#define AVR32_IRQ_NREQGRP15 1
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#define AVR32_IRQ_ADC 57 /* 0 Analog to Digital Converter */
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#define AVR32_IRQ_BASEIRQGRP16 58
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#define AVR32_IRQ_NREQGRP16 0
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/* Group 17 */
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#define AVR32_IRQ_BASEIRQGRP17 58
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#define AVR32_IRQ_NREQGRP17 1
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#define AVR32_IRQ_USBB 58 /* 0 USB 2.0 Interface USBB */
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/* Group 18 */
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#define AVR32_IRQ_BASEIRQGRP18 59
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#define AVR32_IRQ_NREQGRP18 1
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#define AVR32_IRQ_ABDAC 59 /* 0 Audio Bitstream DAC */
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/* Total number of IRQ numbers */
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#define AVR32_IRQ_BADVECTOR 60 /* Not a real IRQ number */
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#define NR_IRQS 60
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/* GPIO IRQ Numbers *********************************************************/
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/* These numbers correspond to GPIO port numbers that have interrupts
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* enabled. These are all decoded by the AVR32_IRQ_GPIO interrupt handler.
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* A lot of effort was made here to keep the number of IRQs to a minimum
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* since it will correspond to various, internal table sizes.
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*/
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/* Up to 32 GPIO interrupts in PORTA0-31 */
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#define __IRQ_GPPIO_PA0 0
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00000001) != 0
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# define AVR32_IRQ_GPIO_PA0 __IRQ_GPPIO_PA0
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# define __IRQ_GPIO_PA1 (__IRQ_GPPIO_PA0+1)
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#else
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# define __IRQ_GPIO_PA1 __IRQ_GPPIO_PA0
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00000002) != 0
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# define AVR32_IRQ_GPIO_PA1 __IRQ_GPIO_PA1
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# define __IRQ_GPIO_PA2 (__IRQ_GPIO_PA1+1)
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#else
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# define __IRQ_GPIO_PA2 __IRQ_GPIO_PA1
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00000004) != 0
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# define AVR32_IRQ_GPIO_PA2 __IRQ_GPIO_PA2
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# define __IRQ_GPIO_PA3 (__IRQ_GPIO_PA2+1)
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#else
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# define __IRQ_GPIO_PA3 __IRQ_GPIO_PA2
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00000008) != 0
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# define AVR32_IRQ_GPIO_PA3 __IRQ_GPIO_PA3
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# define __IRQ_GPIO_PA4 (__IRQ_GPIO_PA3+1)
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#else
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# define __IRQ_GPIO_PA4 __IRQ_GPIO_PA3
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00000010) != 0
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# define AVR32_IRQ_GPIO_PA4 __IRQ_GPIO_PA4
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# define __IRQ_GPIO_PA5 (__IRQ_GPIO_PA4+1)
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#else
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# define __IRQ_GPIO_PA5 __IRQ_GPIO_PA4
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00000020) != 0
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# define AVR32_IRQ_GPIO_PA5 __IRQ_GPIO_PA5
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# define __IRQ_GPIO_PA6 (__IRQ_GPIO_PA5+1)
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#else
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# define __IRQ_GPIO_PA6 __IRQ_GPIO_PA5
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00000040) != 0
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# define AVR32_IRQ_GPIO_PA6 __IRQ_GPIO_PA6
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# define __IRQ_GPIO_PA7 (__IRQ_GPIO_PA6+1)
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#else
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# define __IRQ_GPIO_PA7 __IRQ_GPIO_PA6
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00000080) != 0
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# define AVR32_IRQ_GPIO_PA7 __IRQ_GPIO_PA7
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# define __IRQ_GPIO_PA8 (__IRQ_GPIO_PA7+1)
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#else
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# define __IRQ_GPIO_PA8 __IRQ_GPIO_PA7
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00000100) != 0
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# define AVR32_IRQ_GPIO_PA8 __IRQ_GPIO_PA8
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# define __IRQ_GPIO_PA9 (__IRQ_GPIO_PA8+1)
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#else
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# define __IRQ_GPIO_PA9 __IRQ_GPIO_PA8
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00000200) != 0
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# define AVR32_IRQ_GPIO_PA9 __IRQ_GPIO_PA9
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# define __IRQ_GPIO_PA10 (__IRQ_GPIO_PA9+1)
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#else
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# define __IRQ_GPIO_PA10 __IRQ_GPIO_PA9
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00000400) != 0
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# define AVR32_IRQ_GPIO_PA10 __IRQ_GPIO_PA10
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# define __IRQ_GPIO_PA11 (__IRQ_GPIO_PA10+1)
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#else
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# define __IRQ_GPIO_PA11 __IRQ_GPIO_PA10
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00000800) != 0
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# define AVR32_IRQ_GPIO_PA11 __IRQ_GPIO_PA11
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# define __IRQ_GPIO_PA12 (__IRQ_GPIO_PA11+1)
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#else
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# define __IRQ_GPIO_PA12 __IRQ_GPIO_PA11
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00001000) != 0
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# define AVR32_IRQ_GPIO_PA12 __IRQ_GPIO_PA12
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# define __IRQ_GPIO_PA13 (__IRQ_GPIO_PA12+1)
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#else
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# define __IRQ_GPIO_PA13 __IRQ_GPIO_PA12
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00002000) != 0
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# define AVR32_IRQ_GPIO_PA13 __IRQ_GPIO_PA13
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# define __IRQ_GPIO_PA14 (__IRQ_GPIO_PA13+1)
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#else
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# define __IRQ_GPIO_PA14 __IRQ_GPIO_PA13
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00004000) != 0
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# define AVR32_IRQ_GPIO_PA14 __IRQ_GPIO_PA14
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# define __IRQ_GPIO_PA15 (__IRQ_GPIO_PA14+1)
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#else
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# define __IRQ_GPIO_PA15 __IRQ_GPIO_PA14
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00008000) != 0
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# define AVR32_IRQ_GPIO_PA15 __IRQ_GPIO_PA15
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# define __IRQ_GPIO_PA16 (__IRQ_GPIO_PA15+1)
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#else
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# define __IRQ_GPIO_PA16 __IRQ_GPIO_PA15
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00010000) != 0
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# define AVR32_IRQ_GPIO_PA16 __IRQ_GPIO_PA16
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# define __IRQ_GPIO_PA17 (__IRQ_GPIO_PA16+1)
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#else
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# define __IRQ_GPIO_PA17 __IRQ_GPIO_PA16
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00020000) != 0
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# define AVR32_IRQ_GPIO_PA17 __IRQ_GPIO_PA17
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# define __IRQ_GPIO_PA18 (__IRQ_GPIO_PA17+1)
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#else
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# define __IRQ_GPIO_PA18 __IRQ_GPIO_PA17
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00040000) != 0
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# define AVR32_IRQ_GPIO_PA18 __IRQ_GPIO_PA18
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# define __IRQ_GPIO_PA19 (__IRQ_GPIO_PA18+1)
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#else
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# define __IRQ_GPIO_PA19 __IRQ_GPIO_PA18
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00080000) != 0
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# define AVR32_IRQ_GPIO_PA19 __IRQ_GPIO_PA19
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# define __IRQ_GPIO_PA20 (__IRQ_GPIO_PA19+1)
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#else
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# define __IRQ_GPIO_PA20 __IRQ_GPIO_PA19
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00100000) != 0
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# define AVR32_IRQ_GPIO_PA20 __IRQ_GPIO_PA20
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# define __IRQ_GPIO_PA21 (__IRQ_GPIO_PA20+1)
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#else
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# define __IRQ_GPIO_PA21 __IRQ_GPIO_PA20
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00200000) != 0
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# define AVR32_IRQ_GPIO_PA21 __IRQ_GPIO_PA21
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# define __IRQ_GPIO_PA22 (__IRQ_GPIO_PA21+1)
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#else
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# define __IRQ_GPIO_PA22 __IRQ_GPIO_PA21
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00400000) != 0
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# define AVR32_IRQ_GPIO_PA22 __IRQ_GPIO_PA22
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# define __IRQ_GPIO_PA23 (__IRQ_GPIO_PA22+1)
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#else
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# define __IRQ_GPIO_PA23 __IRQ_GPIO_PA22
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x00800000) != 0
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# define AVR32_IRQ_GPIO_PA23 __IRQ_GPIO_PA23
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# define __IRQ_GPIO_PA24 (__IRQ_GPIO_PA23+1)
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#else
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# define __IRQ_GPIO_PA24 __IRQ_GPIO_PA23
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#endif
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x01000000) != 0
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# define AVR32_IRQ_GPIO_PA24 __IRQ_GPIO_PA24
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# define __IRQ_GPIO_PA25 (__IRQ_GPIO_PA24+1)
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#else
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# define __IRQ_GPIO_PA25 __IRQ_GPIO_PA24
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#endif
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|
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x02000000) != 0
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# define AVR32_IRQ_GPIO_PA25 __IRQ_GPIO_PA25
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# define __IRQ_GPIO_PA26 (__IRQ_GPIO_PA25+1)
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#else
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# define __IRQ_GPIO_PA26 __IRQ_GPIO_PA25
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#endif
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|
|
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x04000000) != 0
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# define AVR32_IRQ_GPIO_PA26 __IRQ_GPIO_PA26
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# define __IRQ_GPIO_PA27 (__IRQ_GPIO_PA26+1)
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#else
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# define __IRQ_GPIO_PA27 __IRQ_GPIO_PA26
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#endif
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|
|
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#if (CONFIG_AVR32_GPIOIRQSETA & 0x08000000) != 0
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|
# define AVR32_IRQ_GPIO_PA27 __IRQ_GPIO_PA27
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|
# define __IRQ_GPIO_PA28 (__IRQ_GPIO_PA27+1)
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|
#else
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|
# define __IRQ_GPIO_PA28 __IRQ_GPIO_PA27
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|
#endif
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|
|
|
#if (CONFIG_AVR32_GPIOIRQSETA & 0x10000000) != 0
|
|
# define AVR32_IRQ_GPIO_PA28 __IRQ_GPIO_PA28
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|
# define __IRQ_GPIO_PA29 (__IRQ_GPIO_PA28+1)
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|
#else
|
|
# define __IRQ_GPIO_PA29 __IRQ_GPIO_PA28
|
|
#endif
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|
|
|
#if (CONFIG_AVR32_GPIOIRQSETA & 0x20000000) != 0
|
|
# define AVR32_IRQ_GPIO_PA29 __IRQ_GPIO_PA29
|
|
# define __IRQ_GPIO_PA30 (__IRQ_GPIO_PA29+1)
|
|
#else
|
|
# define __IRQ_GPIO_PA30 __IRQ_GPIO_PA29
|
|
#endif
|
|
|
|
#if (CONFIG_AVR32_GPIOIRQSETA & 0x40000000) != 0
|
|
# define AVR32_IRQ_GPIO_PA30 __IRQ_GPIO_PA30
|
|
# define __IRQ_GPIO_PA31 (__IRQ_GPIO_PA30+1)
|
|
#else
|
|
# define __IRQ_GPIO_PA31 __IRQ_GPIO_PA30
|
|
#endif
|
|
|
|
#if (CONFIG_AVR32_GPIOIRQSETA & 0x80000000) != 0
|
|
# define AVR32_IRQ_GPIO_PA31 __IRQ_GPIO_PA31
|
|
# define __IRQ_GPIO_PB0 (__IRQ_GPIO_PA31+1)
|
|
#else
|
|
# define __IRQ_GPIO_PB0 __IRQ_GPIO_PA31
|
|
#endif
|
|
|
|
|
|
/* Up to 12 GPIO interrupts in PORTB0-11 */
|
|
|
|
#if (CONFIG_AVR32_GPIOIRQSETB & 0x00000001) != 0
|
|
# define AVR32_IRQ_GPIO_PB0 __IRQ_GPIO_pb0
|
|
# define __IRQ_GPIO_PB1 (__IRQ_GPIO_PB0+1)
|
|
#else
|
|
# define __IRQ_GPIO_PB1 __IRQ_GPIO_PB0
|
|
#endif
|
|
|
|
#if (CONFIG_AVR32_GPIOIRQSETB & 0x00000002) != 0
|
|
# define AVR32_IRQ_GPIO_PB1 __IRQ_GPIO_PB1
|
|
# define __IRQ_GPIO_PB2 (__IRQ_GPIO_PB1+1)
|
|
#else
|
|
# define __IRQ_GPIO_PB2 __IRQ_GPIO_PB1
|
|
#endif
|
|
|
|
#if (CONFIG_AVR32_GPIOIRQSETB & 0x00000004) != 0
|
|
# define AVR32_IRQ_GPIO_PB2 __IRQ_GPIO_PB2
|
|
# define __IRQ_GPIO_PB3 (__IRQ_GPIO_PB2+1)
|
|
#else
|
|
# define __IRQ_GPIO_PB3 __IRQ_GPIO_PB2
|
|
#endif
|
|
|
|
#if (CONFIG_AVR32_GPIOIRQSETB & 0x00000008) != 0
|
|
# define AVR32_IRQ_GPIO_PB3 __IRQ_GPIO_PB3
|
|
# define __IRQ_GPIO_PB4 (__IRQ_GPIO_PB3+1)
|
|
#else
|
|
# define __IRQ_GPIO_PB4 __IRQ_GPIO_PB3
|
|
#endif
|
|
|
|
#if (CONFIG_AVR32_GPIOIRQSETB & 0x00000010) != 0
|
|
# define AVR32_IRQ_GPIO_PB4 __IRQ_GPIO_PB4
|
|
# define __IRQ_GPIO_PB5 (__IRQ_GPIO_PB4+1)
|
|
#else
|
|
# define __IRQ_GPIO_PB5 __IRQ_GPIO_PB4
|
|
#endif
|
|
|
|
#if (CONFIG_AVR32_GPIOIRQSETB & 0x00000020) != 0
|
|
# define AVR32_IRQ_GPIO_PB5 __IRQ_GPIO_PB5
|
|
# define __IRQ_GPIO_PB6 (__IRQ_GPIO_PB5+1)
|
|
#else
|
|
# define __IRQ_GPIO_PB6 __IRQ_GPIO_PB5
|
|
#endif
|
|
|
|
#if (CONFIG_AVR32_GPIOIRQSETB & 0x00000040) != 0
|
|
# define AVR32_IRQ_GPIO_PB6 __IRQ_GPIO_PB6
|
|
# define __IRQ_GPIO_PB7 (__IRQ_GPIO_PB6+1)
|
|
#else
|
|
# define __IRQ_GPIO_PB7 __IRQ_GPIO_PB6
|
|
#endif
|
|
|
|
#if (CONFIG_AVR32_GPIOIRQSETB & 0x00000080) != 0
|
|
# define AVR32_IRQ_GPIO_PB7 __IRQ_GPIO_PB7
|
|
# define __IRQ_GPIO_PB8 (__IRQ_GPIO_PB7+1)
|
|
#else
|
|
# define __IRQ_GPIO_PB8 __IRQ_GPIO_PB7
|
|
#endif
|
|
|
|
#if (CONFIG_AVR32_GPIOIRQSETB & 0x00000100) != 0
|
|
# define AVR32_IRQ_GPIO_PB8 __IRQ_GPIO_PB8
|
|
# define __IRQ_GPIO_PB9 (__IRQ_GPIO_PB8+1)
|
|
#else
|
|
# define __IRQ_GPIO_PB9 __IRQ_GPIO_PB8
|
|
#endif
|
|
|
|
#if (CONFIG_AVR32_GPIOIRQSETB & 0x00000200) != 0
|
|
# define AVR32_IRQ_GPIO_PB9 __IRQ_GPIO_PB9
|
|
# define __IRQ_GPIO_PB10 (__IRQ_GPIO_PB9+1)
|
|
#else
|
|
# define __IRQ_GPIO_PB10 __IRQ_GPIO_PB9
|
|
#endif
|
|
|
|
#if (CONFIG_AVR32_GPIOIRQSETB & 0x00000400) != 0
|
|
# define AVR32_IRQ_GPIO_PB10 __IRQ_GPIO_PB10
|
|
# define __IRQ_GPIO_PB11 (__IRQ_GPIO_PB10+1)
|
|
#else
|
|
# define __IRQ_GPIO_PB11 __IRQ_GPIO_PB10
|
|
#endif
|
|
|
|
#if (CONFIG_AVR32_GPIOIRQSETB & 0x00000800) != 0
|
|
# define AVR32_IRQ_GPIO_PB11 __IRQ_GPIO_PB11
|
|
# define __IRQ_GPIO_PB12 (__IRQ_GPIO_PB11+1)
|
|
#else
|
|
# define __IRQ_GPIO_PB12 __IRQ_GPIO_PB11
|
|
#endif
|
|
|
|
#ifdef CONFIG_AVR32_GPIOIRQ
|
|
# define NR_GPIO_IRQS __IRQ_GPIO_PB12
|
|
#else
|
|
# define NR_GPIO_IRQS 0
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Public Types
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Inline functions
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Public Data
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Public Function Prototypes
|
|
****************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
|
|
#ifdef __cplusplus
|
|
#define EXTERN extern "C"
|
|
extern "C"
|
|
{
|
|
#else
|
|
#define EXTERN extern
|
|
#endif
|
|
|
|
#undef EXTERN
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* __ARCH_AVR_INCLUDE_AT32UC3_IRQ_H */
|