3f65b562bb
inline the up_interrupt_context() to avoid unnecessary stack pushes Signed-off-by: chao.an <anchao@xiaomi.com>
113 lines
3.4 KiB
Plaintext
113 lines
3.4 KiB
Plaintext
############################################################################
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# arch/risc-v/src/qemu-rv32/Make.defs
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#
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# Licensed to the Apache Software Foundation (ASF) under one or more
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# contributor license agreements. See the NOTICE file distributed with
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# this work for additional information regarding copyright ownership. The
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# ASF licenses this file to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance with the
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# License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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#
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############################################################################
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# Specify our HEAD assembly file. This will be linked as
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# the first object file, so it will appear at address 0
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HEAD_ASRC = qemu_rv_head.S
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ifeq ($(CONFIG_BUILD_KERNEL),y)
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STARTUP_OBJS = crt0$(OBJEXT)
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endif
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# Specify our general Assembly files
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CMN_ASRCS += riscv_vectors.S riscv_exception_common.S
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# Specify C code within the common directory to be included
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CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_mtimer.c
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CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
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CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
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CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c
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CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
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CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
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CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
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CMN_CSRCS += riscv_idle.c riscv_tcbinfo.c riscv_cpuidlestack.c
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CMN_CSRCS += riscv_exception.c riscv_getnewintctx.c riscv_doirq.c
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CMN_CSRCS += riscv_saveusercontext.c
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ifeq ($(CONFIG_SMP), y)
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CMN_CSRCS += riscv_cpuindex.c riscv_cpupause.c riscv_cpustart.c
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CMN_ASRCS += riscv_mhartid.S
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endif
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ifeq ($(CONFIG_SCHED_BACKTRACE),y)
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CMN_CSRCS += riscv_backtrace.c
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endif
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ifeq ($(CONFIG_STACK_COLORATION),y)
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CMN_CSRCS += riscv_checkstack.c
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endif
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ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
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CMN_ASRCS += vfork.S
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CMN_CSRCS += riscv_vfork.c
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endif
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ifeq ($(CONFIG_SCHED_THREAD_LOCAL),y)
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CMN_CSRCS += riscv_tls.c
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endif
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ifeq ($(CONFIG_ARCH_FPU),y)
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CMN_ASRCS += riscv_fpu.S
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CMN_CSRCS += riscv_fpucmp.c
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endif
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ifeq ($(CONFIG_ARCH_RV_ISA_A),y)
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CMN_ASRCS += riscv_testset.S
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endif
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ifeq ($(CONFIG_RISCV_SEMIHOSTING_HOSTFS),y)
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CMN_ASRCS += riscv_semihost.S
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CMN_CSRCS += riscv_hostfs.c
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endif
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# Specify our C code within this directory to be included
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CHIP_CSRCS = qemu_rv_start.c qemu_rv_irq_dispatch.c qemu_rv_irq.c
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CHIP_CSRCS += qemu_rv_timerisr.c qemu_rv_allocateheap.c
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ifeq ($(CONFIG_BUILD_KERNEL),y)
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CHIP_CSRCS += qemu_rv_mm_init.c
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endif
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ifneq ($(CONFIG_BUILD_FLAT),y)
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CMN_CSRCS += riscv_task_start.c
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CMN_CSRCS += riscv_pthread_start.c
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CMN_CSRCS += riscv_signal_dispatch.c
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endif
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ifeq ($(CONFIG_ARCH_USE_MPU),y)
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CMN_CSRCS += riscv_pmp.c
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endif
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ifeq ($(CONFIG_ARCH_USE_MMU),y)
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CMN_CSRCS += riscv_mmu.c
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endif
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ifeq ($(CONFIG_ARCH_KERNEL_STACK),y)
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CMN_CSRCS += riscv_addrenv_kstack.c
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endif
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ifeq ($(CONFIG_ARCH_ADDRENV),y)
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CMN_CSRCS += riscv_addrenv.c riscv_pgalloc.c riscv_addrenv_perms.c
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endif
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ifeq ($(CONFIG_MM_PGALLOC),y)
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CHIP_CSRCS += qemu_rv_pgalloc.c
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endif
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