e77b06721b
N/A Summary: Arm64 support for NuttX, Features supported: 1. Cortex-a53 single core and SMP support: it's can run into nsh shell at qemu virt machine. 2. qemu-a53 board configuration support: it's only for evaluate propose 3. FPU support for armv8-a: FPU context switching at NEON/floating-point TRAP is supported. 4. psci interface, armv8 cache operation(data cache) and smccc support. 5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail Note: 1. GCC MACOS issue The GCC 11.2 toolchain for MACOS may get crash while compiling float operation function, the following link describe the issue and give analyse at the issue: https://bugs.linaro.org/show_bug.cgi?id=5825 it's seem GCC give a wrong instruction at certain machine which without architecture features the new toolchain is not available still, so just disable the MACOS cibuild check at present Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
83 lines
2.7 KiB
PHP
83 lines
2.7 KiB
PHP
/****************************************************************************
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* arch/arm64/src/common/macro.inc
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************
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* DESCRIPTION
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* macro define for arm64 assembler
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*
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***************************************************************************/
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#ifndef __ARCH_ARM64_SRC_COMMON_ARM64_MACRO_INC
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#define __ARCH_ARM64_SRC_COMMON_ARM64_MACRO_INC
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/*
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* Get CPU id
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*/
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.macro get_cpu_id xreg0
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mrs \xreg0, mpidr_el1
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/* FIMXME: aff3 not taken into consideration */
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ubfx \xreg0, \xreg0, #0, #24
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.endm
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.macro switch_el, xreg, el3_label, el2_label, el1_label
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mrs \xreg, CurrentEL
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cmp \xreg, 0xc
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beq \el3_label
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cmp \xreg, 0x8
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beq \el2_label
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cmp \xreg, 0x4
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beq \el1_label
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.endm
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/*
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* macro to support mov of immediate constant to 64 bit register
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* It will generate instruction sequence of 'mov'/ 'movz' and one
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* to three 'movk' depending on the immediate value.
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*/
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.macro mov_imm, xreg, imm
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.if ((\imm) == 0)
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mov \xreg, \imm
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.else
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.if (((\imm) >> 31) == 0 || ((\imm) >> 31) == 0x1ffffffff)
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movz \xreg, (\imm >> 16) & 0xffff, lsl 16
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.else
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.if (((\imm) >> 47) == 0 || ((\imm) >> 47) == 0x1ffff)
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movz \xreg, (\imm >> 32) & 0xffff, lsl 32
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.else
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movz \xreg, (\imm >> 48) & 0xffff, lsl 48
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movk \xreg, (\imm >> 32) & 0xffff, lsl 32
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.endif
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movk \xreg, (\imm >> 16) & 0xffff, lsl 16
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.endif
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movk \xreg, (\imm) & 0xffff, lsl 0
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.endif
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.endm
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#define GTEXT(sym) .global sym; .type sym, %function
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#define PERFOPT_ALIGN .balign 4
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#define SECTION_FUNC(sect, sym) \
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.section .sect.sym, "ax"; \
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PERFOPT_ALIGN; sym :
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#define SECTION_SUBSEC_FUNC(sect, subsec, sym) \
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.section .sect.subsec, "ax"; PERFOPT_ALIGN; sym :
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#endif /* __ARCH_ARM64_SRC_COMMON_ARM64_MACRO_INC */
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