264 lines
9.4 KiB
C
264 lines
9.4 KiB
C
/****************************************************************************
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* boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Daniel Pereira Volpato <dpo@certi.org.br>
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*
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* Based on: boards/arm/stm32f0l0g0/nucleo-g071rb/include/board.h
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32F0L0G0_NUCLEO_G070RB_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32F0L0G0_NUCLEO_G070RB_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* HSI - Internal 16 MHz RC Oscillator
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* LSI - 32 KHz RC
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* HSE - 8 MHz from MCO output of ST-LINK (disabled by default)
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul /* 8MHz */
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#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */
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#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
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/* Main PLL Configuration.
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*
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* PLL_VCO = (PLL_SOURCE_FREQUENCY / PLL_M) * PLL_N
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* SYSCLK = PLLCLK = PLLR = PLL_VCO / PLL_DIV_R
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* PLLP = PLL_VCO / PLL_DIV_P
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*
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* Subject to:
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*
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* PLL_SOURCE_FREQUENCY is one of {STM32_HSE_FREQUENCY, STM32_HSI_FREQUENCY}
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*
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* 1 <= PLL_DIV_M <= 8
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* 8 <= PLL_DIV_N <= 86
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* 2 <= PLL_DIV_P <= 32
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* 2 <= PLL_DIV_R <= 8
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* 4 MHz <= PLL_SOURCE_FREQUENCY <= 48 MHz
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* 96 MHz <= PLL_VCO <= 344MHz
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*/
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/* Considering:
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* - PLL_SOURCE_FREQUENCY = STM32_HSI_FREQUENCY = 16,000,000
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* - PLL_DIV_M = 1
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* - PLL_DIV_N = 8
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* - PLL_DIV_R = 2
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* - PLL_DIV_P = 2
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*
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* PLL_VCO = (16,000,000 / 1) * 8 = 128 MHz
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* PLLP = (PLL_VCO / 2) = 64 MHz
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* PLLR = (PLL_VCO / 2) = 64 MHz
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*/
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#define STM32_PLLCFG_PLLSRC RCC_PLLCFG_PLLSRC_HSI
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#define STM32_PLLCFG_PLLCFG (RCC_PLLCFG_PLLPEN | \
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RCC_PLLCFG_PLLREN)
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(8)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP(2)
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#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
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#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 1) * 8)
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#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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/* Use the PLL and set the SYSCLK source to be the PLLR (64 MHz) */
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_SYSCLK_FREQUENCY (STM32_PLLR_FREQUENCY)
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/* AHB clock (HCLK) is SYSCLK (64 MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY
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/* APB1 clock (PCLK1) is HCLK (64 MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
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#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY
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/* Timer clock frequencies */
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/* Timers driven from APB1. Frequency = PCLK1 */
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#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
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/* Timers driven from APB2 is equal to PCLK1 */
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM14_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM15_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM16_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB2_TIM17_CLKIN (STM32_PCLK1_FREQUENCY)
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/* LED definitions **********************************************************/
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/* Nucleo G070RB board has three LEDs. Two of these are controlled by
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* logic on the board and are not available for software control:
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*
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* LD1 COM: LD1 default status is red. LD1 turns to green to indicate that
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* communications are in progress between the PC and the
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* ST-LINK/V2-1.
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* LD3 5V_PWR: green LED indicates that the board is powered by a 5V source.
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*
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* And one can be controlled by software:
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*
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* User LD4: green LED is a user LED connected to STM32 I/O PA5.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in
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* any way. The following definition is used to access the LED.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0 /* User LD4 */
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on the
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* board. The following definitions describe how NuttX controls
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* the LED:
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*
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* SYMBOL Meaning LED1 state
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* ------------------ ----------------------- ----------
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* LED_STARTED NuttX has been started OFF
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* LED_HEAPALLOCATE Heap has been allocated OFF
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* LED_IRQSENABLED Interrupts enabled OFF
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* LED_STACKCREATED Idle stack created ON
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* LED_INIRQ In an interrupt No change
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* LED_SIGNAL In a signal handler No change
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* LED_ASSERTION An assertion failed No change
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* LED_PANIC The system has crashed Blinking
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* LED_IDLE STM32 is is sleep mode Not used
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*/
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 0
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#define LED_IRQSENABLED 0
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#define LED_STACKCREATED 1
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#define LED_INIRQ 2
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#define LED_SIGNAL 2
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#define LED_ASSERTION 2
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#define LED_PANIC 1
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/* Button definitions *******************************************************/
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/* Nucleo G070RB board supports two buttons; only one button is controllable
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* by software:
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*
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* B1 USER: user button connected to STM32 I/O PC13.
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* B2 RESET: push button connected to NRST; used to RESET the MCU.
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*/
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#define BUTTON_USER 0 /* User B1 */
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternate function pin selections ****************************************/
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/* I2C */
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_3 /* PB8 */
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_3 /* PB9 */
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/* TIM */
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#define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1 /* PA8 */
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#define GPIO_TIM1_CH2OUT GPIO_TIM1_CH2OUT_2 /* PB3 */
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#define GPIO_TIM1_CH3OUT GPIO_TIM1_CH3OUT_2 /* PB6 */
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#define GPIO_TIM1_CH4OUT GPIO_TIM1_CH4OUT_1 /* PA11 */
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#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1NOUT_2 /* PB13 */
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#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2NOUT_2 /* PB14 */
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#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3NOUT_2 /* PB15 */
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#define GPIO_TIM3_CH1OUT GPIO_TIM3_CH1OUT_2 /* PB4 */
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#define GPIO_TIM3_CH2OUT GPIO_TIM3_CH2OUT_2 /* PB5 */
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#define GPIO_TIM3_CH3OUT GPIO_TIM3_CH3OUT_1 /* PB0 */
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#define GPIO_TIM3_CH4OUT GPIO_TIM3_CH4OUT_1 /* PB1 */
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#define GPIO_TIM14_CH1OUT GPIO_TIM14_CH1OUT_2 /* PA7 */
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#define GPIO_TIM15_CH1OUT GPIO_TIM15_CH1OUT_3 /* PC1 */
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#define GPIO_TIM15_CH2OUT GPIO_TIM15_CH2OUT_3 /* PC2 */
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#define GPIO_TIM15_CH1NOUT GPIO_TIM15_CH1NOUT_1 /* PA1 */
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#define GPIO_TIM16_CH1OUT GPIO_TIM16_CH1OUT_3 /* PD0 */
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#define GPIO_TIM17_CH1OUT GPIO_TIM17_CH1OUT_2 /* PD1 */
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/* USART */
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/* By default the USART2 is connected to STLINK Virtual COM Port:
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* USART2_RX - PA3
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* USART2_TX - PA2
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*/
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#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
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#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
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/* DMA channels *************************************************************/
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/* ADC */
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/* TODO ADC */
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#endif /* __BOARDS_ARM_STM32F0L0G0_NUCLEO_G070RB_INCLUDE_BOARD_H */
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