110 lines
3.4 KiB
C
110 lines
3.4 KiB
C
/****************************************************************************
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* arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include "riscv_internal.h"
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#include "rv32m1.h"
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#include "hardware/rv32m1_eu.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define RV_IRQ_MASK 27
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* rv32m1_dispatch_irq
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****************************************************************************/
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LOCATE_ITCM
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void *rv32m1_dispatch_irq(uintptr_t vector, uintptr_t *regs)
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{
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uint32_t vec = vector & 0x1f;
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int irq = (vector >> RV_IRQ_MASK) + vec;
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int irqofs = 0;
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if (RV32M1_IRQ_INTMUX0 <= irq)
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{
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uintptr_t chn = irq - RV32M1_IRQ_INTMUX0;
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uintptr_t regaddr = RV32M1_INTMUX_CH_BASE(chn) + INTMUX_CH_VEC_OFFSET;
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uintptr_t regval = getreg32(regaddr);
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/* CH_VEC coudle be 0 while INTMUX doesn't latch pending source
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* interrupts. In that case a spurious interrupt is being serviced,
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* and irq Number shouldn't be compensated.
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*
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* CH_VEC must be checked to account for spurious interrupts.
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*/
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if (regval > 0)
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{
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/* Register VECN[13:2] = 48 x (CPU Vectors + NVIC Vectors) +
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* H(The Highest Interrupt of INTMUX),
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*
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* 1 CPU Vectors for RV32M1 RISCV Cores.
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* No NVIC Vectors for RV32M1 RISCV Cores,
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*
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* H can be obtained easily:
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* H = VECN[13:2] - 48
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*
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* H has to be offset by 8 to skip INTMUX0~7.
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*
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*/
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irqofs = (regval >> 2) - 48 + 8;
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irq += irqofs;
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}
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}
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/* Acknowledge the interrupt */
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riscv_ack_irq(irq);
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/* Deliver the IRQ */
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regs = riscv_doirq(irq, regs);
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if (RV32M1_IRQ_MEXT <= irq)
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{
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irq -= irqofs;
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/* Clear the pending flag */
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putreg32(1 << vec, RV32M1_EU_INTPTPENDCLR);
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}
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return regs;
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}
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