4c601faf6f
Squashed commit of the following:
arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions.
arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0.
arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0.
arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts.
arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls.
arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file.
arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file.
arch/arm/include/stm32f0l0/chip.h: WIP.
arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options.
arch/arm/src/stm32f0l0: Better integrate STM32L0 header files.
nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file.
arch/arm/src/stm32f0l0: Add STM32L0 RCC driver.
arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files.
arch/arm/src/stm32f0l0: Add STM32L0 chip selections.
configs/: Hook new STM32L0 boards into the configuration system.
configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled
configs: add basic support for nucleo-l073rz
configs: add basic support for b-l072z-lrwan1
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| include | ||
| nsh | ||
| scripts | ||
| src | ||
| Kconfig | ||
| README.txt | ||
STATUS
======
05/17: The basic NSH configuration is functional and shows that there is
3-4KB of free heap space. However, attempts to extend this have
failed. I suspect that 8KB of SRAM is insufficient to do much
with the existing NSH configuration. Perhaps some fine tuning
can improve this situation but at this point, I think this board
is only useful for the initial STM32 F0 bring-up, perhaps for
embedded solutions that do not use NSH and for general
experimentation.
There is also support for the Nucleo boards with the STM32 F072
and F092 MCUs. Those ports do not suffer from these problems and
seem to work well in fairly complex configurations. Apparently 8KB
is SRAM is not usable but the parts with larger 16KB and 32KB SRAMs
are better matches.