8682321d0c
Add addrenv support for x86_64. For now we support mapping on PT level, so PD, PDT and PML4 are static Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
129 lines
3.7 KiB
C
129 lines
3.7 KiB
C
/****************************************************************************
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* arch/x86_64/include/arch.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through arch/arch.h
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*/
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#ifndef __ARCH_X86_64_INCLUDE_ARCH_H
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#define __ARCH_X86_64_INCLUDE_ARCH_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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/* Include chip-specific definitions */
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# include <arch/chip/arch.h>
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/* Include architecture-specific definitions */
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#ifdef CONFIG_ARCH_INTEL64
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# include <arch/intel64/arch.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* 4 levels of page table.
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* NOTE: in this implementation:
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* PTL4 index = 0
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* PDPT index = 1
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* PD index = 2
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* PT index = 3
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*/
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#define ARCH_PGT_MAX_LEVELS 4
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#define ARCH_SPGTS (ARCH_PGT_MAX_LEVELS - 1)
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifdef CONFIG_ARCH_ADDRENV
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#ifndef __ASSEMBLY__
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/* The task group resources are retained in a single structure, task_group_s
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* that is defined in the header file nuttx/include/nuttx/sched.h. The type
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* arch_addrenv_t must be defined by platform specific logic in
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* nuttx/arch/<architecture>/include/arch.h.
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*/
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struct arch_addrenv_s
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{
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/* Physical addresses of the static page tables here, these
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* are allocated when a task is created:
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*
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* spgtables[0] - PML4
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* spgtables[1] - PDPT
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* spgtables[2] - PD
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* PT - dynamic allocation
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*/
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uintptr_t spgtables[ARCH_SPGTS];
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/* The text, data, heap bases and heap size here */
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uintptr_t textvbase;
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uintptr_t datavbase;
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uintptr_t heapvbase;
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size_t heapsize;
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/* The page directory root (pml4) is stored in CR3 register */
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uintptr_t cr3;
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};
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typedef struct arch_addrenv_s arch_addrenv_t;
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_ARCH_ADDRENV */
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ARCH_X86_64_INCLUDE_ARCH_H */
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