a9610e16bd
arch/z80/src/ez80/Toolchain.defs: Update some CFLAGS to match CFLAGS from ZDS-II IDE. Apparently, we must say that the CPU is an eZ80F91 event when compiler for eZ80F92. boards/z80/ez80/z20x: Update linker scripts.
70 lines
2.2 KiB
XML
70 lines
2.2 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<Target name="eZ80F920300KITG_RAM" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="../../Schemas/target.tsd" xsi:type="TargetEZ80">
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<Clock>
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<PLL>
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<changeFrequencyOnReset>true</changeFrequencyOnReset>
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<chargePumpFreq>1f4</chargePumpFreq>
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<clockLockCriteria>8</clockLockCriteria>
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<oscFrequency>20000000</oscFrequency>
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</PLL>
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<clockType>PLL</clockType>
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<frequency>20000000</frequency>
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</Clock>
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<ControlReg>
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<pc>0</pc>
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<splStackPtr>100000</splStackPtr>
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<spsStackPtr>ffff</spsStackPtr>
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<useAdlMode>true</useAdlMode>
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</ControlReg>
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<ExtFlash>
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<device />
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<externalAddress>200000</externalAddress>
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<externalAutoSelect>false</externalAutoSelect>
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<externalRamLower>000000</externalRamLower>
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<externalRamUpper>FFFFF</externalRamUpper>
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<manufacturer />
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<units>1</units>
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<usingExternal>false</usingExternal>
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<usingInternal>true</usingInternal>
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</ExtFlash>
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<Memory>
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<ChipSelects>
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<CS0>
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<busMode>0</busMode>
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<controlRegister>8</controlRegister>
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<lower>0</lower>
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<upper>7</upper>
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</CS0>
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<CS1>
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<busMode>0</busMode>
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<controlRegister>0</controlRegister>
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<lower>0</lower>
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<upper>0</upper>
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</CS1>
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<CS2>
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<busMode>0</busMode>
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<controlRegister>0</controlRegister>
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<lower>0</lower>
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<upper>0</upper>
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</CS2>
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<CS3>
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<busMode>0</busMode>
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<controlRegister>0</controlRegister>
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<lower>0</lower>
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<upper>0</upper>
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</CS3>
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</ChipSelects>
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<Internal>
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<mapFlashToPage>0</mapFlashToPage>
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<mapRamToPage>AF</mapRamToPage>
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<useFlashRam>false</useFlashRam>
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<useInternalDataRam>true</useInternalDataRam>
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<useMaccRam>false</useMaccRam>
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</Internal>
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<waitStates>4</waitStates>
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</Memory>
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<cpu>EZ80F92</cpu>
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<schemaVersion>1.0.1</schemaVersion>
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<version>1.00</version>
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</Target>
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