08c4376606
Summary: - ARCH_GLOBAL_IRQDISABLE was initially introduced for LC823450 SMP - At that time, i.MX6 (quad Cortex-A9) did not use this config - However, this option is now used for all CPUs which support SMP - So it's good timing for refactoring the code Impact: - Should have no impact because the logic is the same for SMP Testing: - Tested with board: spresense:smp, spresense:wifi_smp - Tested with qemu: esp32-core:smp, maix-bit:smp, sabre-6quad:smp - Build only: lc823450-xgevk:rndis, sam4cmp-db:nsh Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
108 lines
2.2 KiB
Plaintext
108 lines
2.2 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_RISCV
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comment "RISC-V Options"
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choice
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prompt "RISC-V chip selection"
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default ARCH_CHIP_NR5
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config ARCH_CHIP_FE310
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bool "SiFive FE310"
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select ARCH_RV32IM
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---help---
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SiFive FE310 processor (E31 RISC-V Core with MAC extensions).
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config ARCH_CHIP_K210
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bool "Kendryte K210"
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select ARCH_RV64GC
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select ARCH_HAVE_MPU
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_MULTICPU
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---help---
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Kendryte K210 processor (RISC-V 64bit core with GC extensions)
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config ARCH_CHIP_LITEX
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bool "Enjoy Digital LITEX VEXRISCV"
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select ARCH_RV32IM
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---help---
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Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA).
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config ARCH_CHIP_NR5
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bool "NEXT NanoRisc5"
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select ARCH_RV32IM
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---help---
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NEXT RISC-V NR5Mxx architectures (RISC-V RV32IM cores).
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config ARCH_CHIP_GAP8
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bool "GreenwavesTechnologies GAP8"
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select ARCH_RV32IM
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---help---
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GreenwavesTechnologies GAP8 features a 1+8-core RI5CY DSP-like
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processor, which originally comes from the ETH PULP platform.
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endchoice
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config ARCH_RV32I
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bool
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default n
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config ARCH_RV32IM
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bool
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default n
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config ARCH_RV64GC
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bool
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default n
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select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF
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config ARCH_FAMILY
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string
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default "rv32im" if ARCH_RV32IM
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default "rv64gc" if ARCH_RV64GC
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config ARCH_CHIP
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string
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default "fe310" if ARCH_CHIP_FE310
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default "k210" if ARCH_CHIP_K210
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default "litex" if ARCH_CHIP_LITEX
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default "nr5m100" if ARCH_CHIP_NR5
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default "gap8" if ARCH_CHIP_GAP8
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config NR5_MPU
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bool "MPU support"
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default n
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depends on ARCH_HAVE_MPU
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select ARCH_USE_MPU
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---help---
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Build in support for the RISC-V Memory Protection Unit (MPU).
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Check your chip specifications first; not all RISC-V architectures
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support the MPU.
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if ARCH_RV32IM
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source arch/risc-v/src/rv32im/Kconfig
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endif
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if ARCH_RV64GC
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source arch/risc-v/src/rv64gc/Kconfig
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endif
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if ARCH_CHIP_FE310
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source arch/risc-v/src/fe310/Kconfig
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endif
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if ARCH_CHIP_K210
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source arch/risc-v/src/k210/Kconfig
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endif
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if ARCH_CHIP_LITEX
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source arch/risc-v/src/litex/Kconfig
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endif
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if ARCH_CHIP_NR5
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source arch/risc-v/src/nr5m100/Kconfig
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endif
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if ARCH_CHIP_GAP8
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source arch/risc-v/src/gap8/Kconfig
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endif
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endif
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