70 lines
3.1 KiB
C
70 lines
3.1 KiB
C
/****************************************************************************
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* arch/risc-v/src/bl602/hardware/bl602_cci.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CCI_H
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#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CCI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "bl602_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define BL602_CCI_CFG_OFFSET 0x000000 /* cci_cfg */
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#define BL602_CCI_ADDR_OFFSET 0x000004 /* cci_addr */
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#define BL602_CCI_WDATA_OFFSET 0x000008 /* cci_wdata */
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#define BL602_CCI_RDATA_OFFSET 0x00000c /* cci_rdata */
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#define BL602_CCI_CTL_OFFSET 0x000010 /* cci_ctl */
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/* Register definitions *****************************************************/
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#define BL602_CCI_CFG (BL602_CCI_BASE + BL602_CCI_CFG_OFFSET)
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#define BL602_CCI_ADDR (BL602_CCI_BASE + BL602_CCI_ADDR_OFFSET)
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#define BL602_CCI_WDATA (BL602_CCI_BASE + BL602_CCI_WDATA_OFFSET)
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#define BL602_CCI_RDATA (BL602_CCI_BASE + BL602_CCI_RDATA_OFFSET)
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#define BL602_CCI_CTL (BL602_CCI_BASE + BL602_CCI_CTL_OFFSET)
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/* Register bit definitions *************************************************/
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#define CCI_CFG_REG_MCCI_CLK_INV (1 << 9)
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#define CCI_CFG_REG_SCCI_CLK_INV (1 << 8)
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#define CCI_CFG_CFG_CCI1_PRE_READ (1 << 7)
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#define CCI_CFG_REG_DIV_M_CCI_SCLK_SHIFT (5)
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#define CCI_CFG_REG_DIV_M_CCI_SCLK_MASK (0x03 << CCI_CFG_REG_DIV_M_CCI_SCLK_SHIFT)
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#define CCI_CFG_REG_M_CCI_SCLK_EN (1 << 4)
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#define CCI_CFG_CCI_MAS_HW_MODE (1 << 3)
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#define CCI_CFG_CCI_MAS_SEL_CCI2 (1 << 2)
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#define CCI_CFG_CCI_SLV_SEL_CCI2 (1 << 1)
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#define CCI_CFG_CCI_EN (1 << 0)
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#define CCI_CTL_AHB_STATE_SHIFT (2)
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#define CCI_CTL_AHB_STATE_MASK (0x03 << CCI_CTL_AHB_STATE_SHIFT)
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#define CCI_CTL_CCI_READ_FLAG (1 << 1)
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#define CCI_CTL_CCI_WRITE_FLAG (1 << 0)
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#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CCI_H */
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