238 lines
8.3 KiB
C
238 lines
8.3 KiB
C
/****************************************************************************
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* boards/arm/stm32/nucleo-f412zg/include/board.h
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Konstantin Berezenko <kpberezenko@gmail.com>
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*
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* based on boards/nucleo-f4x1re/include/board.h
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#include <stm32.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* HSE - 8 MHz Crystal
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* LSE - not installed
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*/
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#define STM32_BOARD_USEHSE 1
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#define STM32_BOARD_XTAL 8000000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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/* Main PLL Configuration */
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
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#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC(0) /* HSE or HSI depending on PLLSRC of PLLCFGR*/
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#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLL
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#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
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#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
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#define STM32_SYSCLK_FREQUENCY 96000000ul
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/* AHB clock (HCLK) is SYSCLK (96MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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/* APB1 clock (PCLK1) is HCLK/2 (48MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK (96MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
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/* Timers driven from APB2 will be PCLK2 since no prescale division */
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
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/* Alternate function pin selections ****************************************/
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/* USART2:
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* RXD: PD6 CN9 pin 4
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* TXD: PD5 CN9 pin 6
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*/
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# define GPIO_USART2_RX GPIO_USART2_RX_2
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# define GPIO_USART2_TX GPIO_USART2_TX_2
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/* USART6:
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* RXD: PG9 CN10 pin 16
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* TXD: PG14 CN10 pin 14
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*/
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#define GPIO_USART6_RX GPIO_USART6_RX_2
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#define GPIO_USART6_TX GPIO_USART6_TX_2
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/* I2C1:
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* SCL: PB8 CN7 pin2
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* SDA: PB9 CN7 pin4
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*/
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
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#define GPIO_I2C1_SCL_GPIO \
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(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8)
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#define GPIO_I2C1_SDA_GPIO \
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(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9)
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/* SPI1:
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* MISO: PA6 CN7 pin 12
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* MOSI: PA7 CN7 pin 14
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* SCK: PA5 CN7 pin 10
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*/
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
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/* CAN1:
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* RX: PD0 CN9 pin 25
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* TX: PD1 CN9 pin 27
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*/
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#define GPIO_CAN1_RX GPIO_CAN1_RX_3
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#define GPIO_CAN1_TX GPIO_CAN1_TX_3
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/* LEDs
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*
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* The NUCLEO-F412ZG board has 3 user leds.
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* LD1: PB0 GREEN
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* LD2: PB7 BLUE
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* LD3: PB14 RED
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*/
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#define BOARD_NLEDS 3
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#define GPIO_LD1 \
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(GPIO_PORTB | GPIO_PIN0 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \
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GPIO_SPEED_50MHz)
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#define GPIO_LD2 \
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(GPIO_PORTB | GPIO_PIN7 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \
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GPIO_SPEED_50MHz)
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#define GPIO_LD3 \
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(GPIO_PORTB | GPIO_PIN14 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \
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GPIO_SPEED_50MHz)
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/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is defined in
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* include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
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* events as follows when the red LED (PE24) is available:
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*
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* SYMBOL Meaning
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* ------------------- -----------------------
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* LED_STARTED NuttX has been started
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* LED_HEAPALLOCATE Heap has been allocated
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* LED_IRQSENABLED Interrupts enabled
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* LED_STACKCREATED Idle stack created
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* LED_INIRQ In an interrupt
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* LED_SIGNAL In a signal handler
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* LED_ASSERTION An assertion failed
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* LED_PANIC The system has crashed
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* LED_IDLE MCU is is sleep mode
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*
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* Thus if LD2, NuttX has successfully booted and is, apparently, running
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* normally. If LD2 is flashing at approximately 2Hz, then a fatal error
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* has been detected and the system has halted.
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*/
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#define LED_STARTED 1
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#define LED_HEAPALLOCATE 0
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#define LED_IRQSENABLED 0
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#define LED_STACKCREATED 3
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#define LED_INIRQ 0
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#define LED_SIGNAL 0
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#define LED_ASSERTION 1
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#define LED_PANIC 1
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#endif /* __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H */
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