core0 may write the data used by other cpu, this will cause cache inconsistency. so need fulsh dcache before start other cpus. Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
core0 may write the data used by other cpu, this will cause cache inconsistency. so need fulsh dcache before start other cpus. Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>