405 lines
14 KiB
C
405 lines
14 KiB
C
/************************************************************************************
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* configs/nucleo-144/include/board.h
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* Mark Olsson <post@markolsson.se>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __CONFIG_NUCLEO_144_INCLUDE_BOARD_H
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#define __CONFIG_NUCLEO_144_INCLUDE_BOARD_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#ifdef __KERNEL__
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#include "stm32_rcc.h"
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#ifdef CONFIG_STM32F7_SDMMC1
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# include "stm32_sdmmc.h"
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#endif
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#endif
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* The Nucleo-144 board provides the following clock sources:
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*
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* MCO: 8 MHz from MCO output of ST-LINK is used as input clock
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* X2: 32.768 KHz crystal for LSE
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* X3: HSE crystal oscillator (not provided)
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*
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* So we have these clock source available within the STM32
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*
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* HSI: 16 MHz RC factory-trimmed
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* LSI: 32 KHz RC
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* HSE: 8 MHz from MCO output of ST-LINK
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* LSE: 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE = 8,000,000
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*
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* Subject to:
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*
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* 2 <= PLLM <= 63
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* 192 <= PLLN <= 432
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* 192 MHz <= PLL_VCO <= 432MHz
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*
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* SYSCLK = PLL_VCO / PLLP
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* Subject to
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*
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* PLLP = {2, 4, 6, 8}
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* SYSCLK <= 216 MHz
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*
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* USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
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* Subject to
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* The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
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* and the random number generator need a frequency lower than or equal
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* to 48 MHz to work correctly.
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*
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* 2 <= PLLQ <= 15
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*/
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/* Highest SYSCLK with USB OTG FS clock = 48 MHz
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*
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* PLL_VCO = (8,000,000 / 4) * 216 = 432 MHz
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* SYSCLK = 432 MHz / 2 = 216 MHz
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* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48MHz
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(216)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
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#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 216)
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#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
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/* Configure factors for PLLSAI clock */
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#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
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#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
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/* Configure Dedicated Clock Configuration Register */
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#define STM32_RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ(1)
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#define STM32_RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ(1)
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#define STM32_RCC_DCKCFGR_SAI1SRC RCC_DCKCFGR_SAI1SRC_PLLSAI
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#define STM32_RCC_DCKCFGR_SAI2SRC RCC_DCKCFGR_SAI2SRC_PLLSAI
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#define STM32_RCC_DCKCFGR_TIMPRE 0
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#define STM32_RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_SAI1SRC_PLL
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#define STM32_RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_SAI2SRC_PLL
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/* Configure factors for PLLI2S clock */
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#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
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/* Configure Dedicated Clock Configuration Register 2 */
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#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
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#define STM32_RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_HSI
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#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLLSAI
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#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
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#define STM32_RCC_DCKCFGR2_SPDIFRXSEL RCC_DCKCFGR2_SPDIFRXSEL_PLL
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/* Several prescalers allow the configuration of the two AHB buses, the
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* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
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* frequency of the two AHB buses is 216 MHz while the maximum frequency of
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* the high-speed APB domains is 108 MHz. The maximum allowed frequency of
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* the low-speed APB domain is 54 MHz.
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*/
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/* AHB clock (HCLK) is SYSCLK (216 MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* FLASH wait states
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*
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* --------- ---------- -----------
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* VDD MAX SYSCLK WAIT STATES
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* --------- ---------- -----------
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* 1.7-2.1 V 180 MHz 8
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* 2.1-2.4 V 216 MHz 9
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* 2.4-2.7 V 216 MHz 8
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* 2.7-3.6 V 216 MHz 7
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* --------- ---------- -----------
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*/
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#define BOARD_FLASH_WAITSTATES 7
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/* LED definitions ******************************************************************/
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/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a Blue
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* LED and LD3 a Red LED, that can be controlled by software. The following
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* definitions assume the default Solder Bridges are installed.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
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* The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_LED3 2
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#define BOARD_NLEDS 3
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#define BOARD_LED_GREEN BOARD_LED1
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#define BOARD_LED_BLUE BOARD_LED2
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#define BOARD_LED_RED BOARD_LED3
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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#define BOARD_LED3_BIT (1 << BOARD_LED3)
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/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
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* include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related
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* events as follows:
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*
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*
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* SYMBOL Meaning LED state
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* Red Green Blue
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* ---------------------- -------------------------- ------ ------ ----*/
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#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
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#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
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#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */
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#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */
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#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */
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#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */
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#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */
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#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */
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#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */
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/* Thus if the Green LED is statically on, NuttX has successfully booted and
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* is, apparently, running normally. If the Red LED is flashing at
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* approximately 2Hz, then a fatal error has been detected and the system
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* has halted.
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*/
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/* Button definitions ***************************************************************/
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/* The STM32F7 Discovery supports one button: Pushbutton B1, labeled "User", is
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* connected to GPIO PI11. A high value will be sensed when the button is depressed.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternate function pin selections ************************************************/
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#if defined(CONFIG_NUCLEO_CONSOLE_ARDUINO)
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/* USART6:
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*
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* These configurations assume that you are using a standard Arduio RS-232 shield
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* with the serial interface with RX on pin D0 and TX on pin D1:
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*
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* -------- ---------------
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* STM32F7
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* ARDUIONO FUNCTION GPIO
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* -- ----- --------- -----
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* DO RX USART6_RX PG9
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* D1 TX USART6_TX PG14
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* -- ----- --------- -----
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*/
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# define GPIO_USART6_RX GPIO_USART6_RX_2
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# define GPIO_USART6_TX GPIO_USART6_TX_2
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#endif
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/* USART3:
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* Use USART3 and the USB virtual COM port
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*/
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#if defined(CONFIG_NUCLEO_CONSOLE_VIRTUAL)
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# define GPIO_USART3_RX GPIO_USART3_RX_3
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# define GPIO_USART3_TX GPIO_USART3_TX_3
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#endif
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/* USART8:
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*
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* This configurations assume that you are connecting to the Morpho connector
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* with the serial interface with the adaptor's RX on pin CN11 pin 64 and
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* TX on pin CN11 pin 61
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*
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* USART8: has no remap
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*/
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/* SPI
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*
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*
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* PA6 MISO CN12-13
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* PA7 MOSI CN12-15
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* PA5 SCK CN12-11
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*
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* PB14 MISO CN12-28
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* PB15 MOSI CN12-26
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* PB10 SCK CN12-25
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*
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* PB4 MISO CN12-27
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* PB5 MOSI CN12-29
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* PB3 SCK CN12-31
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*/
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2
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#define GPIO_SPI3_MISO GPIO_SPI3_MISO_1
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#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2
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#define GPIO_SPI3_SCK GPIO_SPI3_SCK_1
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/* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins:
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*
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* STM32 F7 BOARD LAN8742A
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* GPIO SIGNAL PIN NAME
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* -------- ------------ -------------
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* PG11 RMII_TX_EN TXEN
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* PG13 RMII_TXD0 TXD0
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* PG14 RMII_TXD1 TXD1
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* PC4 RMII_RXD0 RXD0/MODE0
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* PC5 RMII_RXD1 RXD1/MODE1
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* PG2 RMII_RXER RXER/PHYAD0 -- Not used
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* PA7 RMII_CRS_DV CRS_DV/MODE2
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* PC1 RMII_MDC MDC
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* PA2 RMII_MDIO MDIO
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* N/A NRST nRST
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* PA1 RMII_REF_CLK nINT/REFCLK0
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* N/A OSC_25M XTAL1/CLKIN
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*
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* The PHY address is either 0 or 1, depending on the state of PG2 on reset.
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* PG2 is not controlled but appears to result in a PHY address of 0.
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*/
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#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2
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#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2
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#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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/************************************************************************************
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* Name: stm32_boardinitialize
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*
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* Description:
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* All STM32 architectures must provide the following entry point. This entry point
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* is called early in the initialization -- after all memory has been configured
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* and mapped but before any devices have been initialized.
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*
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************************************************************************************/
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void stm32_boardinitialize(void);
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __CONFIG_NUCLEO_144_INCLUDE_BOARD_H */
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