..
a1x
Standardize the width of all comment boxes in header files
2015-10-02 17:42:29 -06:00
am335x
arch/arm/include/amm335x: Trivial, cosmetic changes after review
2019-01-08 08:15:04 -06:00
arm
Update TODO list regarding non-queuing of signal actions; Add comments in code at areas where the issue applies.
2019-02-04 08:35:03 -06:00
armv6-m
Update TODO list regarding non-queuing of signal actions; Add comments in code at areas where the issue applies.
2019-02-04 08:35:03 -06:00
armv7-a
Update TODO list regarding non-queuing of signal actions; Add comments in code at areas where the issue applies.
2019-02-04 08:35:03 -06:00
armv7-m
Update TODO list regarding non-queuing of signal actions; Add comments in code at areas where the issue applies.
2019-02-04 08:35:03 -06:00
armv7-r
Update TODO list regarding non-queuing of signal actions; Add comments in code at areas where the issue applies.
2019-02-04 08:35:03 -06:00
c5471
Standardize the width of all comment boxes in header files
2015-10-02 17:42:29 -06:00
dm320
Standardize the width of all comment boxes in header files
2015-10-02 17:42:29 -06:00
efm32
In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
2018-12-03 17:41:59 -06:00
imx1
i.MX6: Add IRQ header file
2016-02-28 14:07:53 -06:00
imx6
Fix lots of typos in C comments and Kconfig help text
2018-07-08 18:24:45 -06:00
imxrt
In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
2018-12-03 17:41:59 -06:00
kinetis
Merged in dagar/nuttx/pr-kinetic_minor_fix (pull request #820 )
2019-01-19 15:39:46 +00:00
kl
arch/: Clean up some naming and spacing.
2018-06-20 15:38:06 -06:00
lc823450
In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
2018-12-03 17:41:59 -06:00
lpc11xx
In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
2018-12-03 17:41:59 -06:00
lpc17xx
In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
2018-12-03 17:41:59 -06:00
lpc31xx
Standardize the width of all comment boxes in header files
2015-10-02 17:42:29 -06:00
lpc43xx
In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
2018-12-03 17:41:59 -06:00
lpc54xx
In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
2018-12-03 17:41:59 -06:00
lpc214x
Fix names of pre-processor variables used in header file idempotence
2016-08-06 18:48:45 -06:00
lpc2378
Fix names of pre-processor variables used in header file idempotence
2016-08-06 18:48:45 -06:00
max326xx
In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
2018-12-03 17:41:59 -06:00
moxart
Standardize the width of all comment boxes in header files
2015-10-02 17:42:29 -06:00
nrf52
In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
2018-12-03 17:41:59 -06:00
nuc1xx
Cosmetic changes to spacing and comments.
2017-04-20 14:08:08 -06:00
sam34
In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
2018-12-03 17:41:59 -06:00
sama5
Standardize the width of all comment boxes in header files
2015-10-02 17:42:29 -06:00
samd2l2
Rename all usage of samdl/SAMDL to samd2l2/SAMD2L2 to make room in the name space for the forthcoming samd5e5/SAMD5E5
2018-07-22 15:54:12 -06:00
samd5e5
configs/metro-m4: Fix RxD interrupt pin selection. The number SERCOM interrupts do not refer to PAD numbers, but to bit positions in the INFLAG register (very tiny footnote in the data sheet). With with final fix, the basic NSH configuration appears fully functional.
2018-09-01 15:29:22 -06:00
samv7
In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
2018-12-03 17:41:59 -06:00
stm32
Merged in raiden00/nuttx_pe (pull request #796 )
2019-01-02 12:12:28 +00:00
stm32f0l0
Merged in raiden00/nuttx_lora (pull request #811 )
2019-01-12 07:59:31 +00:00
stm32f7
In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
2018-12-03 17:41:59 -06:00
stm32h7
Merged in raiden00/nuttx_h7 (pull request #835 )
2019-03-01 17:37:22 +00:00
stm32l4
In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
2018-12-03 17:41:59 -06:00
str71x
Clean up and review of header files for conformance to standards
2015-06-12 19:26:01 -06:00
tiva
arch/arm/include/tiva and src/tiva: Improve GPIO interrupt support by removing unnecessary, hard-coded per-MCU defines and using the existing Kconfig configuration options instead.
2018-12-31 07:19:30 -06:00
tms570
arch/arm/include/tms570, arm/src/armv7-r, and arm/src/tms570: Adds support for the TMS570LS3137ZWT and corrects seversl ARMv7-R and TMS570 issues
2018-04-18 08:58:36 -06:00
xmc4
In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.
2018-12-03 17:41:59 -06:00
.gitignore
Move LPC17xx IOCON register definitions from lpc17_gpio.h to lpc17_iocon.h; fix a few more .gitignore files
2013-04-04 18:12:44 -06:00
arch.h
Standardize the width of all comment boxes in header files
2015-10-02 17:42:29 -06:00
elf.h
arch/arm/include/syscall.h: Add missing inclusion of arch/armv7-r/syscall.h for CortexR.
2019-01-26 07:43:31 -06:00
inttypes.h
Add architecture-specific inttypes.h
2016-10-27 16:01:38 -04:00
irq.h
Squashed commit of the following:
2017-10-09 13:11:17 -06:00
limits.h
Make some file section headers more consistent with standard
2015-04-08 08:04:12 -06:00
spinlock.h
armv7-a, armv7-r, armv7-m: Add atomic read-add-write and read-subtract-write functions.
2018-02-04 12:22:03 -06:00
stdarg.h
Add a generic GCC stdarg.h header file
2012-07-08 14:50:43 +00:00
syscall.h
arch/arm/include/syscall.h: Add missing inclusion of arch/armv7-r/syscall.h for CortexR.
2019-01-26 07:43:31 -06:00
tls.h
TLS: Forgot to add a file before last commit
2016-03-11 12:30:04 -06:00
types.h
Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore()
2016-02-14 16:11:25 -06:00
4ae7373427