a9d713bbcc
Squashed commit of the following:
arch/arm/src/samd5e5: Clean-up EIC logic.
arch/arm/src/samd5e5: Fix some compilation issues; Still issues with the EIC logic from samd2x.
arch/arm/src/samd5e5: Fix some compilation issues; bring in some EIC logic from samd2x.
arch/arm/src/samd5e5: Add NVMCTRL header file, fix some compiler problems, misc. clean-up.
configs/metro-m4: Add LED support.
arch/arm/src/samd5e5: Bring in SAML21 clock configuration. This is a WIP; it cannot possible even compile yet.
arch/arm/src/samd5e5: Leverage Cortex-M4 interrupt and SysTick logic from the SAM3/4.
arch/arm/src/samd5e5: Add SERCOM utility function.
arch/arm/src/samd5e5: Bring all SERCOM USART logic from SAMD2L2 to SAMD5E5. This is a brute coy with nothing more than more that name changes and extension from 5 to 7 SERCOMs.
arch/arm/src/samd5e5: Add sam_config.h header file
arch/arm/src/samd5e5/: Add Generic Clock (GCLK) utility functions.
arch/arm/src/samd5e5: Add EVSYS register definition file
arch/arm/src/samd5e5 and configs/metro-m4: Use SERCOM3 for the Arduino serial shield as console.
arch/arm/src/samd5e5/chip: Add SERCOM USART, SPI, I2C master, and slave register defintions header files
arch/arm/src/samd5e5/chip: Add AES, PM, TRNG, and WDT header files.
arch/arm/src/samd5e5/chip: Add pin multiplexing header files.
Various fixes to configuration system; fix metro-m4/nsh defconfig file.
configs/metro-m4: Add initial support for the Adafruit Metro M4 board.
arch/arm/src/samd5e5: Add peripheral clock helpers.
arch/arm/src/samd5e5/chip: Add PAC register definition header file. Fix some errors in the memory map header file.
arch/arm/src/samd5e5: Add chip.h headerf file.
arch/arm/src/samd5e5: Add PORT register definitions and support from SAML21.
arch/arm/include/samd5e5: Add interrupt vector definitions.
arch/arm/src/samd5e5: Add some boilerplate files. Correct some typos.
arch/arm/src/samd5e5/chip/sam_eic.h: Add EIC register definitions.
arch/arm/src/samd5e5/chip: Add OSC32KCTRL and OSCCTRL register definitions.
arch/arm/src/samd5e5/chip: Add GCLK, MCLK, and RSTC header files.
arch/arm/src/samd5e5/chip/sam_cmcc.h: Add CMCC register definitions
arch/arm/src/samd5e5/chip/sam_supc.h: Add SUPC header file.
arch/arm/src/samd5e5: Add start-up logic.
arch/arm/src/samd5e5: Add Make.defs file
arch/arm/src/samd5e5/chip: Add memory map header file.
arch/arm/include/samd5e5: Add chip.h header file.
arch/arm/Kconfig and arch/arm/src/samd5e5/Kconfig: Add configuration logic for the SAMD5x/Ex family.
97 lines
4.6 KiB
C
97 lines
4.6 KiB
C
/********************************************************************************************
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* arch/arm/src/samd5e5/chip/sam_trng.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_TRNG_H
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#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_TRNG_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/sam_memorymap.h"
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* TRNG register offsets ********************************************************************/
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#define SAM_TRNG_CTRLA_OFFSET 0x0000 /* Control A register */
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#define SAM_TRNG_EVCTRL_OFFSET 0x0004 /* Event control register */
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#define SAM_TRNG_INTENCLR_OFFSET 0x0008 /* Interrupt enable clear register */
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#define SAM_TRNG_INTENSET_OFFSET 0x0009 /* Interrupt enable set register */
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#define SAM_TRNG_INTFLAG_OFFSET 0x000a /* Interrupt flag and status clear register */
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#define SAM_TRNG_DATA_OFFSET 0x0020 /* Output data register */
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/* TRNG register addresses ******************************************************************/
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#define SAM_TRNG_CTRLA (SAM_TRNG_BASE+SAM_TRNG_CTRLA_OFFSET)
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#define SAM_TRNG_EVCTRL (SAM_TRNG_BASE+SAM_TRNG_EVCTRL_OFFSET)
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#define SAM_TRNG_INTENCLR (SAM_TRNG_BASE+SAM_TRNG_INTENCLR_OFFSET)
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#define SAM_TRNG_INTENSET (SAM_TRNG_BASE+SAM_TRNG_INTENSET_OFFSET)
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#define SAM_TRNG_INTFLAG (SAM_TRNG_BASE+SAM_TRNG_INTFLAG_OFFSET)
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#define SAM_TRNG_DATA (SAM_TRNG_BASE+SAM_TRNG_DATA_OFFSET)
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/* TRNG register bit definitions ************************************************************/
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/* Control register */
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#define TRNG_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
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#define TRNG_CTRLA_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
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/* Event control register, Interrupt enable clear, interrupt enable set register, interrupt
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* flag status registers.
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*/
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#define TRNG_EVCTRL_DATARDYEO (1 << 0) /* Bit 0: Data ready event output */
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/* Data register (32-bit data) */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_TRNG_H */
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