138 lines
3.9 KiB
C
138 lines
3.9 KiB
C
/****************************************************************************
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* arch/risc-v/src/fe310/fe310_clockconfig.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "riscv_internal.h"
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#include "fe310_clockconfig.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define EXT_OSC 16000000
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#define PLL_64M (1 + (31 << 4) + (3 << 10)) /* R:2 F:64 Q:8 8M/512M/64M */
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#define PLL_128M (1 + (31 << 4) + (2 << 10)) /* R:2 F:64 Q:4 8M/512M/128M */
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#define PLL_256M (1 + (31 << 4) + (1 << 10)) /* R:2 F:64 Q:2 8M/512M/256M */
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: fe310_get_hfclk
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****************************************************************************/
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uint32_t fe310_get_hfclk(void)
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{
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uint32_t val;
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uint32_t freq = 0;
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/* Check pllbypass */
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if (0 != (getreg32(FE310_PLLCFG) & PLLCFG_PLLBYPASS))
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{
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freq = EXT_OSC;
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goto out;
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}
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/* Check pllsel */
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if (0 != ((val = getreg32(FE310_PLLCFG)) & PLLCFG_PLLSEL))
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{
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freq = EXT_OSC;
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freq /= ((val & 0x3) + 1); /* R: 2bit */
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freq *= ((((val >> 4) & 0x3f) + 1) * 2); /* F: 6bit */
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freq /= (1 << ((val >> 10) & 0x3)); /* Q: 2bit */
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goto out;
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}
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/* TODO: HFROSC */
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PANIC();
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out:
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return freq;
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}
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/****************************************************************************
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* Name: fe310_clockconfig
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****************************************************************************/
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void fe310_clockconfig(void)
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{
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uint32_t val;
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uint32_t pllsel;
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/* NOTE: These are workarounds to avoid a bug with debugger */
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pllsel = 0x1;
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pllsel <<= 16;
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/* Disable PLL by setting pllbypass and clear pllsel */
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modifyreg32(FE310_PLLCFG, pllsel, PLLCFG_PLLBYPASS);
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/* Enable HFXOSC (external Xtal OSC 16MHz) and wait */
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putreg32(HFXOSCCFG_HFXOSCEN, FE310_HFXOSCCFG);
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while ((getreg32(FE310_HFXOSCCFG) & HFXOSCCFG_HFXOSCRDY)
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!= HFXOSCCFG_HFXOSCRDY)
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{
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}
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val = PLL_256M;
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val |= (PLLCFG_PLLREFSEL); /* Set PLLREFSEL (XOSCOUT) */
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val |= PLLCFG_PLLBYPASS; /* But Still disable PLL */
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putreg32(val, FE310_PLLCFG); /* Set PLL config */
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/* Set plloutdiv to pass-through */
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putreg32(0x1 << 8, FE310_PLLOUTDIV);
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/* Enable PLL by clearing pllbypass and wait */
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modifyreg32(FE310_PLLCFG, PLLCFG_PLLBYPASS, 0);
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while ((getreg32(FE310_PLLCFG) & PLLCFG_PLLLOCK) == 0x0)
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{
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}
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/* TODO: Set QSPI divider if needed */
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/* Select PLL as hfclk */
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modifyreg32(FE310_PLLCFG, 0, pllsel);
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}
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