483 lines
15 KiB
C
483 lines
15 KiB
C
/****************************************************************************
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* libs/libc/machine/arm/armv7-r/arch_elf.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <inttypes.h>
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#include <stdlib.h>
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#include <errno.h>
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#include <debug.h>
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#include <arch/elf.h>
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#include <nuttx/elf.h>
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_checkarch
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*
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* Description:
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* Given the ELF header in 'hdr', verify that the ELF file is appropriate
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* for the current, configured architecture. Every architecture that uses
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* the ELF loader must provide this function.
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*
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* Input Parameters:
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* hdr - The ELF header read from the ELF file.
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*
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* Returned Value:
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* True if the architecture supports this ELF file.
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*
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****************************************************************************/
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bool up_checkarch(const Elf32_Ehdr *ehdr)
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{
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/* Make sure it's an ARM executable */
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if (ehdr->e_machine != EM_ARM)
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{
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berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine);
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return false;
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}
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/* Make sure that 32-bit objects are supported */
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if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
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{
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berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n",
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ehdr->e_ident[EI_CLASS]);
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return false;
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}
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/* Verify endian-ness */
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#ifdef CONFIG_ENDIAN_BIG
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if (ehdr->e_ident[EI_DATA] != ELFDATA2MSB)
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#else
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if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
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#endif
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{
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berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n",
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ehdr->e_ident[EI_DATA]);
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return false;
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}
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/* Make sure the entry point address is properly aligned */
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#ifdef CONFIG_ARM_THUMB
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if ((ehdr->e_entry & 2) != 0)
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#else
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if ((ehdr->e_entry & 3) != 0)
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#endif
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{
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berr("ERROR: Entry point is not properly aligned: %08" PRIx32 "\n",
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ehdr->e_entry);
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return false;
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}
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/* TODO: Check ABI here. */
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return true;
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}
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/****************************************************************************
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* Name: up_relocate and up_relocateadd
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*
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* Description:
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* Perform an architecture-specific ELF relocation. Every architecture
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* that uses the ELF loader must provide this function.
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*
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* Input Parameters:
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* rel - The relocation type
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* sym - The ELF symbol structure containing the fully resolved value.
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* There are a few relocation types for a few architectures that do
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* not require symbol information. For those, this value will be
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* NULL. Implementations of these functions must be able to handle
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* that case.
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* addr - The address that requires the relocation.
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*
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* Returned Value:
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* Zero (OK) if the relocation was successful. Otherwise, a negated errno
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* value indicating the cause of the relocation failure.
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*
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****************************************************************************/
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int up_relocate(const Elf32_Rel *rel, const Elf32_Sym *sym, uintptr_t addr)
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{
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int32_t offset;
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unsigned int relotype;
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#ifdef CONFIG_ARM_THUMB
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uint32_t upper_insn;
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uint32_t lower_insn;
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#endif
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/* All relocations except R_ARM_V4BX depend upon having valid symbol
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* information.
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*/
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relotype = ELF32_R_TYPE(rel->r_info);
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if (sym == NULL && relotype != R_ARM_NONE && relotype != R_ARM_V4BX)
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{
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return -EINVAL;
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}
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/* Handle the relocation by relocation type */
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switch (relotype)
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{
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case R_ARM_NONE:
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{
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/* No relocation */
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}
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break;
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case R_ARM_PC24:
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case R_ARM_CALL:
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case R_ARM_JUMP24:
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{
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binfo("Performing PC24 [%" PRId32 "] link "
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"at addr %08lx [%08lx] to sym '%p' st_value=%08lx\n",
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ELF32_R_TYPE(rel->r_info), (long)addr,
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(long)(*(uint32_t *)addr),
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sym, (long)sym->st_value);
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offset = (*(uint32_t *)addr & 0x00ffffff) << 2;
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if (offset & 0x02000000)
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{
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offset -= 0x04000000;
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}
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offset += sym->st_value - addr;
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#ifdef CONFIG_ARM_THUMB
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if ((offset & 2) != 0 || offset < (int32_t) 0xfe000000 ||
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#else
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if ((offset & 3) != 0 || offset < (int32_t) 0xfe000000 ||
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#endif
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offset >= (int32_t) 0x02000000)
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{
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berr("ERROR: PC24 [%" PRId32 "] relocation out of range, "
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"offset=%08lx\n",
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ELF32_R_TYPE(rel->r_info), offset);
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return -EINVAL;
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}
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offset >>= 2;
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*(uint32_t *)addr &= 0xff000000;
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*(uint32_t *)addr |= offset & 0x00ffffff;
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}
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break;
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case R_ARM_ABS32:
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case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
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{
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binfo("Performing ABS32 link "
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"at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
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(long)addr, (long)(*(uint32_t *)addr), sym,
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(long)sym->st_value);
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*(uint32_t *)addr += sym->st_value;
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}
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break;
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case R_ARM_V4BX:
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{
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binfo("Performing V4BX link at addr=%08lx [%08lx]\n",
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(long)addr, (long)(*(uint32_t *)addr));
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/* Preserve only Rm and the condition code */
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*(uint32_t *)addr &= 0xf000000f;
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/* Change instruction to 'mov pc, Rm' */
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*(uint32_t *)addr |= 0x01a0f000;
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}
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break;
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case R_ARM_PREL31:
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{
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binfo("Performing PREL31 link "
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"at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
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(long)addr, (long)(*(uint32_t *)addr), sym,
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(long)sym->st_value);
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offset = *(uint32_t *)addr + sym->st_value - addr;
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*(uint32_t *)addr = offset & 0x7fffffff;
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}
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break;
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case R_ARM_MOVW_ABS_NC:
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case R_ARM_MOVT_ABS:
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{
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binfo("Performing MOVx_ABS [%" PRId32 "] link "
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"at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
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ELF32_R_TYPE(rel->r_info), (long)addr,
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(long)(*(uint32_t *)addr),
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sym, (long)sym->st_value);
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offset = *(uint32_t *)addr;
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offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff);
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offset += sym->st_value;
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if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS)
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{
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offset >>= 16;
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}
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*(uint32_t *)addr &= 0xfff0f000;
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*(uint32_t *)addr |= ((offset & 0xf000) << 4) | (offset & 0x0fff);
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}
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break;
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#ifdef CONFIG_ARM_THUMB
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case R_ARM_THM_MOVW_ABS_NC:
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case R_ARM_THM_MOVT_ABS:
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{
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/* Thumb BL and B.W instructions. Encoding:
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*
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* upper_insn:
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*
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* 1 1 1 1 1 1
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* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Instruction
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* +----------+---+--------------------------+----------+
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* |1 1 1 |OP1| OP2 | | 32-Bit
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* +----------+---+--+-----+-----------------+----------+
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* |1 1 1 | 1 0| i |1 0 1 1 0 0 | imm4 | MOVT
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* +----------+------+-----+-----------------+----------+
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*
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* lower_insn:
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*
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* 1 1 1 1 1 1
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* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Instructions
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* +---+-------------------------------------------------+
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* |OP | | 32-Bit
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* +---+----------+--------+-----------------------------+
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* |0 | imm3 | Rd | imm8 | MOVT
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* +---+----------+--------+-----------------------------+
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*
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* The 16-bit immediate value is encoded in these bits:
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*
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* i = imm16[11] = upper_insn[10]
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* imm4 = imm16[12:15] = upper_insn[3:0]
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* imm3 = imm16[8:10] = lower_insn[14:12]
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* imm8 = imm16[0:7] = lower_insn[7:0]
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*/
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upper_insn = (uint32_t)(*(uint16_t *)addr);
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lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
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binfo("Performing THM_MOVx [%" PRId32 "] link "
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"at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
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ELF32_R_TYPE(rel->r_info), (long)addr,
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(int)upper_insn, (int)lower_insn,
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sym, (long)sym->st_value);
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/* Extract the 16-bit offset from the 32-bit instruction */
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offset = ((upper_insn & 0x000f) << 12) | /* imm4 -> imm16[8:10] */
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((upper_insn & 0x0400) << 1) | /* i -> imm16[11] */
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((lower_insn & 0x7000) >> 4) | /* imm3 -> imm16[8:10] */
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(lower_insn & 0x00ff); /* imm8 -> imm16[0:7] */
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/* And perform the relocation */
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binfo(" offset=%08" PRIx32 " branch target=%08" PRIx32 "\n",
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offset, offset + sym->st_value);
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offset += sym->st_value;
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/* Update the immediate value in the instruction.
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* For MOVW we want the bottom 16-bits; for MOVT we want
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* the top 16-bits.
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*/
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if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS)
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{
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offset >>= 16;
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}
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upper_insn = ((upper_insn & 0xfbf0) | ((offset & 0xf000) >> 12) |
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((offset & 0x0800) >> 1));
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*(uint16_t *)addr = (uint16_t)upper_insn;
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lower_insn = ((lower_insn & 0x8f00) | ((offset & 0x0700) << 4) |
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(offset & 0x00ff));
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*(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
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binfo(" insn [%04x %04x]\n",
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(int)upper_insn, (int)lower_insn);
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}
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break;
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case R_ARM_THM_CALL:
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case R_ARM_THM_JUMP24:
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{
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uint32_t S;
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uint32_t J1;
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uint32_t J2;
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/* Thumb BL and B.W instructions. Encoding:
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*
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* upper_insn:
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*
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* 1 1 1 1 1 1
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* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Instructions
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* +----------+---+--------------------------+----------+
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* |1 1 1 |OP1| OP2 | | 32-Bit
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* +----------+---+--+-----+-----------------+----------+
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* |1 1 1 | 1 0| S | imm10 | BL
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* +----------+------+-----+----------------------------+
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*
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* lower_insn:
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*
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* 1 1 1 1 1 1
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* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Instructions
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* +---+------------------------------------------------+
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* |OP | | 32-Bit
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* +---+--+---+---+---+---------------------------------+
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* |1 1 |J1 | 1 |J2 | imm11 | BL
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* +------+---+---+---+--------------------------------+
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*
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* The branch target is encoded in these bits:
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*
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* S = upper_insn[10]
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* imm10 = upper_insn[0:9]
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* imm11 = lower_insn[0:10]
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* J1 = lower_insn[13]
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* J2 = lower_insn[11]
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*/
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upper_insn = (uint32_t)(*(uint16_t *)addr);
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lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
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binfo("Performing THM_JUMP24 [%" PRId32 "] link "
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"at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
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ELF32_R_TYPE(rel->r_info), (long)addr,
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(int)upper_insn, (int)lower_insn,
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sym, (long)sym->st_value);
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/* Extract the 25-bit offset from the 32-bit instruction:
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*
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* offset[24] = S
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* offset[23] = ~(J1 ^ S)
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* offset[22] = ~(J2 ^ S)]
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* offset[12:21] = imm10
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* offset[1:11] = imm11
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* offset[0] = 0
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*/
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S = (upper_insn >> 10) & 1;
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J1 = (lower_insn >> 13) & 1;
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J2 = (lower_insn >> 11) & 1;
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offset = (S << 24) | /* S - > offset[24] */
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((~(J1 ^ S) & 1) << 23) | /* J1 -> offset[23] */
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((~(J2 ^ S) & 1) << 22) | /* J2 -> offset[22] */
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((upper_insn & 0x03ff) << 12) | /* imm10 -> offset[12:21] */
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((lower_insn & 0x07ff) << 1); /* imm11 -> offset[1:11] */
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/* 0 -> offset[0] */
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/* Sign extend */
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if (offset & 0x01000000)
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{
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offset -= 0x02000000;
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}
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/* And perform the relocation */
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binfo(" S=%" PRId32 " J1=%" PRId32 " J2=%" PRId32
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" offset=%08" PRIx32 " branch target=%08" PRIx32 "\n",
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S, J1, J2, offset, offset + sym->st_value - addr);
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offset += sym->st_value - addr;
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/* Is this a function symbol? If so, then the branch target must be
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* an odd Thumb address
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*/
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if (ELF32_ST_TYPE(sym->st_info) == STT_FUNC && (offset & 1) == 0)
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{
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berr("ERROR: ERROR: JUMP24 [%" PRId32 "] "
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"requires odd offset, offset=%08" PRIx32 "\n",
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ELF32_R_TYPE(rel->r_info), offset);
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return -EINVAL;
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}
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/* Check the range of the offset */
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if (offset < (int32_t)0xff000000 || offset >= (int32_t)0x01000000)
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{
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berr("ERROR: ERROR: JUMP24 [%" PRId32 "] "
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"relocation out of range, branch target=%08" PRIx32 "\n",
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ELF32_R_TYPE(rel->r_info), offset);
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return -EINVAL;
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}
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/* Now, reconstruct the 32-bit instruction using the new, relocated
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* branch target.
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*/
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S = (offset >> 24) & 1;
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J1 = S ^ (~(offset >> 23) & 1);
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J2 = S ^ (~(offset >> 22) & 1);
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upper_insn = ((upper_insn & 0xf800) | (S << 10) |
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((offset >> 12) & 0x03ff));
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*(uint16_t *)addr = (uint16_t)upper_insn;
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lower_insn = ((lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) |
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((offset >> 1) & 0x07ff));
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*(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
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binfo(" S=%" PRId32 " J1=%" PRId32 " J2=%" PRId32
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" insn [%04" PRIx32 " %04" PRIx32 "]\n",
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S, J1, J2, upper_insn, lower_insn);
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}
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break;
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#endif /* CONFIG_ARM_THUMB */
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default:
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berr("ERROR: Unsupported relocation: %" PRId32 "\n",
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ELF32_R_TYPE(rel->r_info));
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return -EINVAL;
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}
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return OK;
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}
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int up_relocateadd(const Elf32_Rela *rel, const Elf32_Sym *sym,
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uintptr_t addr)
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{
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berr("ERROR: RELA relocation not supported\n");
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return -ENOSYS;
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}
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