a763ed1e07
This commit ensures that RTC data is properly allocated in the RTC segment in the linker. This fixes the reported problem about using the legacy bootloader and RTC.
307 lines
7.6 KiB
Plaintext
307 lines
7.6 KiB
Plaintext
/****************************************************************************
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* boards/risc-v/esp32c3-legacy/common/scripts/mcuboot_sections.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Default entry point: */
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ENTRY(__start);
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SECTIONS
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{
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.metadata :
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{
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/* Magic for load header */
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LONG(0xace637d3)
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/* Application entry point address */
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KEEP(*(.entry_addr))
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/* IRAM metadata:
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* - Destination address (VMA) for IRAM region
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* - Flash offset (LMA) for start of IRAM region
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* - Size of IRAM region
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*/
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LONG(ADDR(.iram0.text))
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LONG(LOADADDR(.iram0.text))
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LONG(SIZEOF(.iram0.text))
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/* DRAM metadata:
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* - Destination address (VMA) for DRAM region
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* - Flash offset (LMA) for start of DRAM region
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* - Size of DRAM region
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*/
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LONG(ADDR(.dram0.data))
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LONG(LOADADDR(.dram0.data))
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LONG(SIZEOF(.dram0.data))
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} >metadata
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_image_drom_vma = ADDR(.flash.rodata);
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_image_drom_lma = LOADADDR(.flash.rodata);
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_image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma;
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.flash.rodata :
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{
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_srodata = ABSOLUTE(.);
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*(EXCLUDE_FILE (*libarch.a:esp32c3_spiflash.* esp32c3_head.* esp32c3_start.*) .rodata)
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*(EXCLUDE_FILE (*libarch.a:esp32c3_spiflash.* esp32c3_head.* esp32c3_start.*) .rodata.*)
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*(.srodata.*)
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*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
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*(.xt_except_table)
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*(.gcc_except_table .gcc_except_table.*)
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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. = (. + 3) & ~ 3;
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__eh_frame = ABSOLUTE(.);
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KEEP(*(.eh_frame))
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. = (. + 7) & ~ 3;
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/* C++ constructor and destructor tables, properly ordered: */
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_sinit = ABSOLUTE(.);
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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_einit = ABSOLUTE(.);
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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/* C++ exception handlers table: */
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__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
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*(.xt_except_desc)
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*(.gnu.linkonce.h.*)
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__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
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*(.xt_except_desc_end)
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*(.dynamic)
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*(.gnu.version_d)
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. = ALIGN(4); /* This table MUST be 4-byte aligned */
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_erodata = ABSOLUTE(.);
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/* Literals are also RO data. */
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_lit4_start = ABSOLUTE(.);
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*(*.lit4)
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*(.lit4.*)
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*(.gnu.linkonce.lit4.*)
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_lit4_end = ABSOLUTE(.);
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. = ALIGN(4);
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} >drom0_0_seg AT>ROM
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.iram0.text :
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{
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_iram_start = ABSOLUTE(.);
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/* Vectors go to start of IRAM */
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KEEP(*(.exception_vectors.text));
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. = ALIGN(4);
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*(.iram1)
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*(.iram1.*)
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*libarch.a:esp32c3_spiflash.*(.literal .text .literal.* .text.*)
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esp32c3_head.*(.literal .text .literal.* .text.*)
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esp32c3_start.*(.literal .text .literal.* .text.*)
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*(.wifi0iram .wifi0iram.*)
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*(.wifirxiram .wifirxiram.*)
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*(.wifislpiram .wifislpiram.*)
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*(.wifislprxiram .wifislprxiram.*)
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} >iram0_0_seg AT>ROM
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.dram0.dummy (NOLOAD):
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{
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/* This section is required to skip .iram0.text area because iram0_0_seg
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* and dram0_0_seg reflect the same address space on different buses.
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*/
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. = ORIGIN(dram0_0_seg) + _iram_end - _iram_start;
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} >dram0_0_seg
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.noinit (NOLOAD):
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{
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/* This section contains data that is not initialized during load,
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* or during the application's initialization sequence.
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*/
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. = ALIGN(8);
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*(.noinit)
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*(.noinit.*)
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. = ALIGN(8);
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} >dram0_0_seg
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.dram0.data :
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{
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/* .data initialized on power-up in ROMed configurations. */
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_sdata = ABSOLUTE(.);
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KEEP (*(.data))
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KEEP (*(.data.*))
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KEEP (*(.gnu.linkonce.d.*))
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KEEP (*(.data1))
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__global_pointer$ = . + 0x800;
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KEEP (*(.sdata))
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KEEP (*(.sdata.*))
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KEEP (*(.gnu.linkonce.s.*))
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KEEP (*(.sdata2))
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KEEP (*(.sdata2.*))
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KEEP (*(.gnu.linkonce.s2.*))
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KEEP (*(.jcr))
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*(.dram1 .dram1.*)
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*libarch.a:esp32c3_spiflash.*(.rodata .rodata.*)
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esp32c3_head.*(.rodata .rodata.*)
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esp32c3_start.*(.rodata .rodata.*)
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_edata = ABSOLUTE(.);
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. = ALIGN(4);
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} >dram0_0_seg AT>ROM
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/* Shared RAM */
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.dram0.bss (NOLOAD) :
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{
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/* .bss initialized on power-up */
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. = ALIGN (8);
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_sbss = ABSOLUTE(.);
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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*(.sbss2)
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*(.sbss2.*)
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*(.gnu.linkonce.sb2.*)
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*(.dynbss)
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KEEP (*(.bss))
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*(.bss.*)
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*(.share.mem)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(8);
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_ebss = ABSOLUTE(.);
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} >dram0_0_seg
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/* Marks the end of IRAM code segment */
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.iram0.text_end (NOLOAD) :
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{
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. = ALIGN (16);
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} >iram0_0_seg
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.iram0.data :
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{
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. = ALIGN(16);
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*(.iram.data)
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*(.iram.data*)
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} >iram0_0_seg AT>ROM
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.iram0.bss (NOLOAD) :
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{
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. = ALIGN(16);
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*(.iram.bss)
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*(.iram.bss*)
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. = ALIGN(16);
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_iram_end = ABSOLUTE(.);
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} >iram0_0_seg
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_image_irom_vma = ADDR(.flash.text);
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_image_irom_lma = LOADADDR(.flash.text);
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_image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma;
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/* The alignment of the ".flash.text" output section is forced to
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* 0x0000FFFF (64KB) to ensure that it will be allocated at the beginning
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* of the next available Flash block.
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* This is required to meet the following constraint from the external
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* flash MMU:
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* VMA % 64KB == LMA % 64KB
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* i.e. the lower 16 bits of both the virtual address (address seen by the
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* CPU) and the load address (physical address of the external flash) must
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* be equal.
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*/
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.flash_text_dummy (NOLOAD) : ALIGN(0x0000FFFF)
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{
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/* This section is required to skip .flash.rodata area because irom0_0_seg
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* and drom0_0_seg reflect the same address space on different buses.
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*/
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. = SIZEOF(.flash.rodata);
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} >irom0_0_seg
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.flash.text : ALIGN(0x0000FFFF)
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{
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_stext = .;
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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. = ALIGN(4);
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_etext = .;
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} >irom0_0_seg AT>ROM
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.rtc.text :
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{
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. = ALIGN(4);
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*(.rtc.literal .rtc.text)
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} >rtc_seg AT>ROM
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.rtc.dummy (NOLOAD) :
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{
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/* This section is required to skip .rtc.text area because the text and
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* data segments reflect the same address space on different buses.
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*/
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. = SIZEOF(.rtc.text);
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} >rtc_seg
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/* RTC BSS section. */
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.rtc.bss (NOLOAD) :
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{
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*(.rtc.bss)
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} >rtc_seg
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.rtc.data :
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{
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*(.rtc.data)
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*(.rtc.data.*)
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*(.rtc.rodata)
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*(.rtc.rodata.*)
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/* Whatever is left from the RTC memory is used as a special heap. */
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. = ALIGN (4);
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_srtcheap = ABSOLUTE(.);
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} >rtc_seg AT>ROM
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}
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