349 lines
24 KiB
C
349 lines
24 KiB
C
/****************************************************************************
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* arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_FLASH_H
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#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_FLASH_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define STM32_FLASH_ACR_OFFSET 0x0000 /* Access control register */
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#define STM32_FLASH_KEYR1_OFFSET 0x0004 /* Key register for bank 1 */
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#define STM32_FLASH_OPTKEYR_OFFSET 0x0008 /* Option key register */
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#define STM32_FLASH_CR1_OFFSET 0x000c /* Control register for bank 1 */
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#define STM32_FLASH_SR1_OFFSET 0x0010 /* Status register for bank 1 */
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#define STM32_FLASH_CCR1_OFFSET 0x0014 /* Clear control register for bank 1 */
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#define STM32_FLASH_OPTCR_OFFSET 0x0018 /* Option control register */
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#define STM32_FLASH_OPTSR_CUR_OFFSET 0x001c /* Option status register (CUR) */
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#define STM32_FLASH_OPTSR_PRG_OFFSET 0x0020 /* Option status register (PRG) */
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#define STM32_FLASH_OPTCCR_OFFSET 0x0024 /* Option clear control register */
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#define STM32_FLASH_PRAR_CUR1_OFFSET 0x0028 /* Protection address for bank 1 */
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#define STM32_FLASH_PRAR_PRG1_OFFSET 0x002C /* Protection address for bank 1 */
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#define STM32_FLASH_SCAR_CUR1_OFFSET 0x0030 /* Secure address for bank 1 (CUR) */
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#define STM32_FLASH_SCAR_PRG1_OFFSET 0x0034 /* Secure address for bank 1 (PRG) */
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#define STM32_FLASH_WPSN_CUR1R_OFFSET 0x0038 /* Write sector protection for bank 1 (CUR) */
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#define STM32_FLASH_WPSN_PRG1R_OFFSET 0x003C /* Write sector protection for bank 1 (PRG) */
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#define STM32_FLASH_BOOT_CUR_OFFSET 0x0040 /* Boot address (CUR) */
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#define STM32_FLASH_BOOT_PRGR_OFFSET 0x0044 /* Boot address (PRG) */
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#define STM32_FLASH_CRCCR1_OFFSET 0x0050 /* CRC control register for bank 1 */
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#define STM32_FLASH_CRCSADD1R_OFFSET 0x0054 /* CRC start address register for bank 1 */
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#define STM32_FLASH_CRCEADD1R_OFFSET 0x0058 /* CRC end address register for bank 1 */
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#define STM32_FLASH_CRCDATAR_OFFSET 0x005C /* CRC data register */
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#define STM32_FLASH_ECC_FA1R_OFFSET 0x0060 /* ECC fail address register for bank 1 */
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#define STM32_FLASH_KEYR2_OFFSET 0x0104 /* Key register for bank 2 */
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#define STM32_FLASH_CR2_OFFSET 0x010c /* Control register for bank 2 */
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#define STM32_FLASH_SR2_OFFSET 0x0110 /* Status register for bank 2 */
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#define STM32_FLASH_CCR2_OFFSET 0x0114 /* Clear control register for bank 2 */
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#define STM32_FLASH_PRAR_CUR2_OFFSET 0x0128 /* Protection address for bank 2 */
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#define STM32_FLASH_PRAR_PRG2_OFFSET 0x012C /* Protection address for bank 2 */
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#define STM32_FLASH_SCAR_CUR2_OFFSET 0x0130 /* Secure address for bank 2 (CUR) */
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#define STM32_FLASH_SCAR_PRG2_OFFSET 0x0134 /* Secure address for bank 2 (PRG) */
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#define STM32_FLASH_WPSN_CUR2R_OFFSET 0x0138 /* Write sector protection for bank 2 (CUR) */
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#define STM32_FLASH_WPSN_PRG2R_OFFSET 0x013C /* Write sector protection for bank 2 (PRG) */
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#define STM32_FLASH_CRCCR2_OFFSET 0x0150 /* CRC control register for bank 2 */
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#define STM32_FLASH_CRCSADD2R_OFFSET 0x0154 /* CRC start address register for bank 2 */
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#define STM32_FLASH_CRCEADD2R_OFFSET 0x0158 /* CRC end address register for bank 2 */
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#define STM32_FLASH_ECC_FA2R_OFFSET 0x0160 /* ECC fail address register for bank 2 */
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#define STM32_FLASH_BANK1_OFFSET 0x0000 /* Bank 1 registers offset */
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#define STM32_FLASH_BANK2_OFFSET 0x0100 /* Bank 2 registers offset */
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/* Register Addresses *******************************************************/
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#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET)
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#define STM32_FLASH_KEYR1 (STM32_FLASHIF_BASE + STM32_FLASH_KEYR1_OFFSET)
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#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET)
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#define STM32_FLASH_CR1 (STM32_FLASHIF_BASE + STM32_FLASH_CR1_OFFSET)
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#define STM32_FLASH_SR1 (STM32_FLASHIF_BASE + STM32_FLASH_SR1_OFFSET)
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#define STM32_FLASH_CCR1 (STM32_FLASHIF_BASE + STM32_FLASH_CCR1_OFFSET)
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#define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE + STM32_FLASH_OPTCR_OFFSET)
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#define STM32_FLASH_OPTSR_CUR (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR_CUR_OFFSET)
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#define STM32_FLASH_OPTSR_PRG (STM32_FLASHIF_BASE + STM32_FLASH_OPTSR_PRG_OFFSET)
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#define STM32_FLASH_OPTCCR (STM32_FLASHIF_BASE + STM32_FLASH_OPTCCR_OFFSET)
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#define STM32_FLASH_PRAR_CUR1 (STM32_FLASHIF_BASE + STM32_FLASH_PRAR_CUR1_OFFSET)
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#define STM32_FLASH_PRAR_PRG1 (STM32_FLASHIF_BASE + STM32_FLASH_PRAR_PRG1_OFFSET)
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#define STM32_FLASH_SCAR_CUR1 (STM32_FLASHIF_BASE + STM32_FLASH_SCAR_CUR1_OFFSET)
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#define STM32_FLASH_SCAR_PRG1 (STM32_FLASHIF_BASE + STM32_FLASH_SCAR_PRG1_OFFSET)
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#define STM32_FLASH_WPSN_CUR1R (STM32_FLASHIF_BASE + STM32_FLASH_WPSN_CUR1R_OFFSET)
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#define STM32_FLASH_WPSN_PRG1R (STM32_FLASHIF_BASE + STM32_FLASH_WPSN_PRG1R_OFFSET)
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#define STM32_FLASH_BOOT_CUR (STM32_FLASHIF_BASE + STM32_FLASH_BOOT_CUR_OFFSET)
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#define STM32_FLASH_BOOT_PRGR (STM32_FLASHIF_BASE + STM32_FLASH_BOOT_PRGR_OFFSET)
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#define STM32_FLASH_CRCCR1 (STM32_FLASHIF_BASE + STM32_FLASH_CRCCR1_OFFSET)
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#define STM32_FLASH_CRCSADD1R (STM32_FLASHIF_BASE + STM32_FLASH_CRCSADD1R_OFFSET)
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#define STM32_FLASH_CRCEADD1R (STM32_FLASHIF_BASE + STM32_FLASH_CRCEADD1R_OFFSET)
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#define STM32_FLASH_CRCDATAR (STM32_FLASHIF_BASE + STM32_FLASH_CRCDATAR_OFFSET)
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#define STM32_FLASH_ECC_FA1R (STM32_FLASHIF_BASE + STM32_FLASH_ECC_FA1R_OFFSET)
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#define STM32_FLASH_KEYR2 (STM32_FLASHIF_BASE + STM32_FLASH_KEYR2_OFFSET)
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#define STM32_FLASH_CR2 (STM32_FLASHIF_BASE + STM32_FLASH_CR2_OFFSET)
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#define STM32_FLASH_SR2 (STM32_FLASHIF_BASE + STM32_FLASH_SR2_OFFSET)
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#define STM32_FLASH_CCR2 (STM32_FLASHIF_BASE + STM32_FLASH_CCR2_OFFSET)
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#define STM32_FLASH_PRAR_CUR2 (STM32_FLASHIF_BASE + STM32_FLASH_PRAR_CUR2_OFFSET)
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#define STM32_FLASH_PRAR_PRG2 (STM32_FLASHIF_BASE + STM32_FLASH_PRAR_PRG2_OFFSET)
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#define STM32_FLASH_SCAR_CUR2 (STM32_FLASHIF_BASE + STM32_FLASH_SCAR_CUR2_OFFSET)
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#define STM32_FLASH_SCAR_PRG2 (STM32_FLASHIF_BASE + STM32_FLASH_SCAR_PRG2_OFFSET)
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#define STM32_FLASH_WPSN_CUR2R (STM32_FLASHIF_BASE + STM32_FLASH_WPSN_CUR2R_OFFSET)
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#define STM32_FLASH_WPSN_PRG2R (STM32_FLASHIF_BASE + STM32_FLASH_WPSN_PRG2R_OFFSET)
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#define STM32_FLASH_CRCCR2 (STM32_FLASHIF_BASE + STM32_FLASH_CRCCR2_OFFSET)
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#define STM32_FLASH_CRCSADD2R (STM32_FLASHIF_BASE + STM32_FLASH_CRCSADD2R_OFFSET)
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#define STM32_FLASH_CRCEADD2R (STM32_FLASHIF_BASE + STM32_FLASH_CRCEADD2R_OFFSET)
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#define STM32_FLASH_ECC_FA2R (STM32_FLASHIF_BASE + STM32_FLASH_ECC_FA2R_OFFSET)
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/* Register Bitfield Definitions ********************************************/
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/* Flash Access Control Register (ACR) Bank 1 or 2 */
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#define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-3: Latency */
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#define FLASH_ACR_LATENCY_MASK (15 << FLASH_ACR_LATENCY_SHIFT)
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# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */
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# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 0000: Zero wait states */
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# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 0001: One wait state */
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# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 0010: Two wait states */
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# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 0011: Three wait states */
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# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 0100: Four wait states */
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# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 0101: Five wait states */
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# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 0110: Six wait states */
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# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 0111: Seven wait states */
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# define FLASH_ACR_LATENCY_8 (8 << FLASH_ACR_LATENCY_SHIFT) /* 1000: Eight wait states */
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# define FLASH_ACR_LATENCY_9 (9 << FLASH_ACR_LATENCY_SHIFT) /* 1001: Nine wait states */
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# define FLASH_ACR_LATENCY_10 (10 << FLASH_ACR_LATENCY_SHIFT) /* 1010: Ten wait states */
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# define FLASH_ACR_LATENCY_11 (11 << FLASH_ACR_LATENCY_SHIFT) /* 1011: Eleven wait states */
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# define FLASH_ACR_LATENCY_12 (12 << FLASH_ACR_LATENCY_SHIFT) /* 1100: Twelve wait states */
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# define FLASH_ACR_LATENCY_13 (13 << FLASH_ACR_LATENCY_SHIFT) /* 1101: Thirteen wait states */
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# define FLASH_ACR_LATENCY_14 (14 << FLASH_ACR_LATENCY_SHIFT) /* 1110: Fourteen wait states */
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# define FLASH_ACR_LATENCY_15 (15 << FLASH_ACR_LATENCY_SHIFT) /* 1111: Fifteen wait states */
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#define FLASH_ACR_WRHIGHFREQ_SHIFT (4) /* Bitd 4-5: Flash signal delay */
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#define FLASH_ACR_WRHIGHFREQ_MASK (3 << FLASH_ACR_WRHIGHFREQ_SHIFT)
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# define FLASH_ACR_WRHIGHFREQ(n) ((n) << FLASH_ACR_WRHIGHFREQ_SHIFT)
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/* Flash Control Register (CR) Bank 1 or 2 (if different) */
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#define FLASH_CR_LOCK (1 << 0) /* Bit 0: Lock */
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#define FLASH_CR_PG (1 << 1) /* Bit 1: Programming */
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#define FLASH_CR_SER (1 << 2) /* Bit 2: Sector erase */
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#define FLASH_CR_BER (1 << 3) /* Bit 3: Bank erase */
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#define FLASH_CR_PSIZE_SHIFT (4) /* Bits 4-5: Program size */
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#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
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# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* 00: x8 */
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# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* 01: x16 */
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# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* 10: x32 */
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# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* 11: x64 */
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#define FLASH_CR_FW (1 << 6) /* Bit 6: Force write */
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#define FLASH_CR_START (1 << 7) /* Bit 7: Erase start */
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#define FLASH_CR_SNB_SHIFT (8) /* Bits 8-10: Sector number */
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#define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT) /* Used to clear FLASH_CR_SNB bits */
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# define FLASH_CR_SNB(n) ((uint32_t)((n) & 0x7) << FLASH_CR_SNB_SHIFT) /* Sector n, n=0..7 */
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/* Bits 11-13: Reserved */
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#define FLASH_CR_SPSS2 (1 << 14) /* Bit 14: Bank1 Reserved, Bank 2 special sector selection bit */
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#define FLASH_CR_CRCEN (1 << 15) /* Bit 15: CRC control enable */
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#define FLASH_CR_EOPIE (1 << 16) /* Bit 16: End-of-program interrupt enable */
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#define FLASH_CR_WRPERRIE (1 << 17) /* Bit 17: Write protection error interrupt enable */
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#define FLASH_CR_PGSERRIE (1 << 18) /* Bit 18: Programming sequence error interrupt enable */
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#define FLASH_CR_STRBERRIE (1 << 19) /* Bit 19: Strobe error interrupt enable */
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/* Bit 20: Reserved */
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#define FLASH_CR_INCERRIE (1 << 21) /* Bit 21: Inconsistency error interrupt enable */
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#define FLASH_CR_OPERRIE (1 << 22) /* Bit 22: Write/erase error interrupt enable */
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#define FLASH_CR_RDPERRIE (1 << 23) /* Bit 23: Read protection error interrupt enable */
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#define FLASH_CR_RDSERRIE (1 << 24) /* Bit 24: Secure error interrupt enable */
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#define FLASH_CR_SNECCERRIE (1 << 25) /* Bit 25: ECC single correction error interrupt enable */
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#define FLASH_CR_DBECCERRIE (1 << 26) /* Bit 26: ECC double detection error interrupt enable */
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#define FLASH_CR_CRCENDIE (1 << 27) /* Bit 27: CRC end of calculation interrupt enable */
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/* Bits 28-31: Reserved */
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/* Flash Status Register (SR) Bank 1 or 2 */
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#define FLASH_SR_BSY (1 << 0) /* Bit 0: Busy */
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#define FLASH_SR_WBNE (1 << 1) /* Bit 1: write buffer not empty */
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#define FLASH_SR_QW (1 << 2) /* Bit 2: wait queue flag */
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#define FLASH_SR_CRCBUSY (1 << 3) /* Bit 3: CRC busy flag */
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/* Bits 4-15: Reserved */
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#define FLASH_SR_EOP (1 << 16) /* Bit 16: End of program */
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#define FLASH_SR_WROERR (1 << 17) /* Bit 17: Write protection error */
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#define FLASH_SR_PGSERR (1 << 18) /* Bit 18: Programming sequence error */
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#define FLASH_SR_STRBERR (1 << 19) /* Bit 19: Strobe error */
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/* Bit 20: Reserved */
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#define FLASH_SR_INCERR (1 << 21) /* Bit 21: Inconsistency error */
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#define FLASH_SR_OPERR (1 << 22) /* Bit 22: Write/erase error */
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#define FLASH_SR_RDPERR (1 << 23) /* Bit 23: Read protection error */
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#define FLASH_SR_RDSERR (1 << 24) /* Bit 24: Secure error */
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#define FLASH_SR_SNECCERR (1 << 25) /* Bit 25: ECC single error */
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#define FLASH_SR_DBECCERR (1 << 26) /* Bit 26: ECC double detection error */
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#define FLASH_SR_CRCEND (1 << 27) /* Bit 27: CRC end of calculation */
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/* Bits 28-31: Reserved */
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/* Flash Clear control register Bank 1 or 2 */
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/* Bits 0-15: Reserved */
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#define FLASH_CLR_EOP (1 << 16) /* Bit 16: Clear end of program */
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#define FLASH_CLR_WROERR (1 << 17) /* Bit 17: Clear write protection error */
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#define FLASH_CLR_PGSERR (1 << 18) /* Bit 18: Clear programming sequence error */
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#define FLASH_CLR_STRBERR (1 << 19) /* Bit 19: Clear strobe error */
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/* Bit 20: Reserved */
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#define FLASH_CLR_INCERR (1 << 21) /* Bit 21: Clear inconsistency error */
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#define FLASH_CLR_OPERR (1 << 22) /* Bit 22: Clear write/erase error */
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#define FLASH_CLR_RDPERR (1 << 23) /* Bit 23: Clear read protection error */
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#define FLASH_CLR_RDSERR (1 << 24) /* Bit 24: Clear secure error */
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#define FLASH_CLR_SNECCERR (1 << 25) /* Bit 25: Clear ECC single error */
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#define FLASH_CLR_DBECCERR (1 << 26) /* Bit 26: Clear ECC double detection error */
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#define FLASH_CLR_CRCEND (1 << 27) /* Bit 27: Clear CRC end of calculation */
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/* Bits 28-31: Reserved */
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/* Flash Option Control Register (OPTCR) Bank 1 or 2 */
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#define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */
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#define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */
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/* Bits 2-3: Reserved */
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#define FLASH_OPTCR_MER (1 << 4) /* Bit 4: Mass erase */
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/* Bits 5-29: Reserved */
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#define FLASH_OPTCR_CHANGEERRIE (1 << 30) /* Bit 30: Option byte change error interrupt enable */
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#define FLASH_OPTCR_SWAPBANK (1 << 31) /* Bit 31: Bank swapping */
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/* Flash Option Status Register (OPTSR) */
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#define FLASH_OPTSR_BUSYV (1 << 0) /* Bit 0: Option byte change busy */
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/* Bit 1: Reserved */
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#define FLASH_OPTSR_BORLEV_SHIFT (2) /* Bits 2-3: Brownout level option */
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#define FLASH_OPTSR_BORLEV_MASK (3 << FLASH_OPTSR_BORLEV_SHIFT)
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# define FLASH_OPTSR_BORLEV_0 (0 << FLASH_OPTSR_BORLEV_SHIFT)
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# define FLASH_OPTSR_BORLEV_1 (1 << FLASH_OPTSR_BORLEV_SHIFT)
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# define FLASH_OPTSR_BORLEV_2 (2 << FLASH_OPTSR_BORLEV_SHIFT)
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# define FLASH_OPTSR_BORLEV_3 (3 << FLASH_OPTSR_BORLEV_SHIFT)
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#define FLASH_OPTSR_IWDGSW (1 << 4) /* Bit 4: IWDG control mode */
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/* Bit 5: Reserved */
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#define FLASH_OPTSR_NRSTSTOP (1 << 6) /* Bit 6: DStop entry reset */
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#define FLASH_OPTSR_NRSTSTDY (1 << 7) /* Bit 7: DStandby entry reset */
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#define FLASH_OPTSR_RDP_SHIFT (8) /* Bits 8-15: Readout protection level */
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#define FLASH_OPTSR_RDP_MASK (0xff << FLASH_OPTSR_RDP_SHIFT)
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# define FLASH_OPTSR_RDP(n) ((uint32_t)(n) << FLASH_OPTSR_RDP_SHIFT)
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/* Bit 16: Reserved */
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#define FLASH_OPTSR_IWDGFZSTOP (1 << 17) /* Bit 17: IWDG Stop mode freeze */
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#define FLASH_OPTSR_IWDGFZSTBY (1 << 18) /* Bit 18: IWDG Standby mode freeze */
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#define FLASH_OPTSR_STRAMSIZE_SHIFT (19) /* Bits 19-20: ST RAM size */
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#define FLASH_OPTSR_STRAMSIZE_MASK (3 << FLASH_OPTSR_STRAMSIZE_SHIFT)
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# define FLASH_OPTSR_STRAMSIZE_2 (0 << FLASH_OPTSR_STRAMSIZE_SHIFT)
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# define FLASH_OPTSR_STRAMSIZE_4 (1 << FLASH_OPTSR_STRAMSIZE_SHIFT)
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# define FLASH_OPTSR_STRAMSIZE_8 (2 << FLASH_OPTSR_STRAMSIZE_SHIFT)
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# define FLASH_OPTSR_STRAMSIZE_16 (3 << FLASH_OPTSR_STRAMSIZE_SHIFT)
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#define FLASH_OPTSR_SECURITY (1 << 21) /* Bit 21: Security enable*/
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/* Bits 22-28: Reserved */
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#define FLASH_OPTSR_IOHSLV (1 << 29) /* Bit 29: IO high-speed at low-volateg */
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#define FLASH_OPTSR_CHANGEERR (1 << 30) /* Bit 30: Option byte change error */
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#define FLASH_OPTSR_SWAPBANK (1 << 31) /* Bit 31: Bank swapping status */
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/* Flash Option Clear Control Register (OPTCCR) */
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/* Bits 0-29: Reserved */
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#define FLASH_OPTCCR_OPTCHANGEERR (1 << 30) /* Bit 30: OPTCHANGEERR reset */
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/* Bit 31: Reserved */
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/* Flash Protection Address (PRAR) Bank 1 or 2 */
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#define FLASH_PRAR_START_SHIFT (0) /* Bits 0-11 Bank PCROP area start status bits */
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#define FLASH_PRAR_START_MASK (0xfff << FLASH_PRAR_START_SHIFT)
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/* Bits 12-15: Reserved */
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#define FLASH_PRAR_END_SHIFT (16) /* Bits 16-27 Bank PCROP area end configuration bits */
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#define FLASH_PRAR_END_MASK (0xfff << FLASH_PRAR_END_SHIFT)
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/* Bits 28-30: Reserved */
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#define FLASH_PRAR_DMEP (1 << 31) /* Bit 31: Bank PCROP protected erase enable option configuration bit */
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/* Flash Secure Address (SCAR) Bank 1 or 2 */
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#define FLASH_SCAR_START_SHIFT (0) /* Bits 0-11 Bank secure-only area start status bits */
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#define FLASH_SCAR_START_MASK (0xfff << FLASH_SCAR_START_SHIFT)
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/* Bits 12-15: Reserved */
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#define FLASH_SCAR_END_SHIFT (16) /* Bits 16-27 Bank secure-only area end configuration bits */
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#define FLASH_SCAR_END_MASK (0xfff << FLASH_SCAR_END_SHIFT)
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/* Bits 28-30: Reserved */
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#define FLASH_SCAR_DMES (1 << 31) /* Bit 31: Bank secure access protected erase enable option status bit */
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/* Flash Write Sector Protection (WPSN) Bank 1 or 2 */
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#define FLASH_WPSN_WRPSN_SHIFT (0) /* Bits 0-7: Sector write protection option */
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#define FLASH_WPSN_WRPSN_MASK (15 << FLASH_WPSN_WRPSN_SHIFT)
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/* Bits 8-31: Reserved */
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/* Flash Register Boot Address (BOOT) Bank 1 or 2 */
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#define FLASH_BOOT_ADD0_SHIFT (0) /* Bits 0-15: Boot address 0 */
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#define FLASH_BOOT_ADD0_MASK (0xffff << FLASH_BOOT_ADD0_SHIFT)
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#define FLASH_BOOT_ADD1_SHIFT (16) /* Bits 16-31: Boot address 1 */
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#define FLASH_BOOT_ADD1_MASK (0xffff << FLASH_BOOT_ADD1_SHIFT)
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/* Flash CRC Control Register (CRCCR) Bank 1 or 2 */
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#define FLASH_CRCCR_CRC_SEC_SHIFT (0) /* Bits 0-2: Bank 1 CRC sector number */
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#define FLASH_CRCCR_CRC_SEC_MASK (7 << FLASH_CRCCR_CRC_SEC_SHIFT)
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/* Bits 3-6: Reserved */
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#define FLASH_CRCCR_ALL_BANK (1 << 7) /* Bit 7: Bank CRC select bit */
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#define FLASH_CRCCR_CRC_BY_SECT (1 << 8) /* Bit 9: Bank CRC sector mode select bit */
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#define FLASH_CRCCR_ADD_SECT (1 << 9) /* Bit 9: Bank CRC sector select bit */
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#define FLASH_CRCCR_CLEAN_SECT (1 << 10) /* Bit 10: Bank CRC sector list clear bit */
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/* Bits 11-15: Reserved */
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#define FLASH_CRCCR_START_CRC (1 << 16) /* Bit 16: Bank CRC start bit */
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#define FLASH_CRCCR_CLEAN_CRC (1 << 17) /* Bit 16: Bank CRC clean bit */
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#define FLASH_CRCCR_BURST_SHIFT (20) /* Bits 20-21: Bank CRC burst size */
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#define FLASH_CRCCR_BURST_MASK (3 << FLASH_CRCCR_BURST_SHIFT)
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# define FLASH_CRCCR_BURST_4 (0 << FLASH_CRCCR_BURST_SHIFT)
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# define FLASH_CRCCR_BURST_16 (1 << FLASH_CRCCR_BURST_SHIFT)
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# define FLASH_CRCCR_BURST_64 (2 << FLASH_CRCCR_BURST_SHIFT)
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# define FLASH_CRCCR_BURST_256 (3 << FLASH_CRCCR_BURST_SHIFT)
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/* Bits 22-31: Reserved */
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/* Flash CRC Start Address Register (CRCSADDR) Bank 1 or 2 */
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/* Bits 0-1: Reserved */
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#define FLASH_CRCSADDR_START_SHIFT (2) /* Bits 2-19 CRC start address on bank */
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#define FLASH_CRCSADDR_START_MASK (0x3ffff << FLASH_CRCSADDR_START_SHIFT)
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/* Bits 20-31: Reserved */
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/* Flash CRC End Address Register (CRCSEDDR) Bank 1 or 2 */
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/* Bits 0-1: Reserved */
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#define FLASH_CRCSEDDR_START_SHIFT (2) /* Bits 2-19 CRC end address on bank */
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#define FLASH_CRCSEDDR_START_MASK (0x3ffff << FLASH_CRCSEDDR_START_SHIFT)
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/* Bits 20-31: Reserved */
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/* Flash ECC fail Address(FAnR) Bank 1 or 2 */
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#define FLASH_ECC_FAR_SHIFT (0) /* Bits 0-14 Bank 1 ECC error add */
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#define FLASH_ECC_FAR_MASK (0x7fff << FLASH_CRCSEDDR_START_SHIFT)
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/* Bits 15-31: Reserved */
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#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_FLASH_H */
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