89 lines
3.6 KiB
C
89 lines
3.6 KiB
C
/****************************************************************************
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* boards/xtensa/esp32/esp32-core/include/board.h
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __BOARDS_XTENSA_ESP32_ESP32_CORE_INCLUDE_BOARD_H
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#define __BOARDS_XTENSA_ESP32_ESP32_CORE_INCLUDE_BOARD_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The ESP32 Core board V2 is fitted with either a 26 a 40MHz crystal */
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#ifdef CONFIG_ESP32CORE_XTAL_26MHz
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# define BOARD_XTAL_FREQUENCY 26000000
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#else
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# define BOARD_XTAL_FREQUENCY 40000000
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#endif
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/* Clock reconfiguration is currently disabled, so the CPU will be running
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* at the XTAL frequency or at two times the XTAL frequency, depending upon
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* how we load the code:
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*
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* - If we load the code into FLASH at address 0x1000 where it is started by
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* the second level bootloader, then the frequency is the crystal
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* frequency.
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* - If we load the code into IRAM after the second level bootloader has run
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* this frequency will be twice the crystal frequency.
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*
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* Don't ask me for an explanation.
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*/
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/* Note: The bootloader (esp-idf bootloader.bin) configures:
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*
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* - CPU frequency to 80MHz
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* - The XTAL frequency according to the SDK config CONFIG_ESP32_XTAL_FREQ,
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* which is 40MHz by default.
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*
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* Reference:
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* https://github.com/espressif/esp-idf/blob
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* /6fd855ab8d00d23bad4660216bc2122c2285d5be/components
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* /bootloader_support/src/bootloader_clock.c#L38-L62
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*/
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#ifdef CONFIG_ESP32CORE_RUN_IRAM
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# define BOARD_CLOCK_FREQUENCY (2 * BOARD_XTAL_FREQUENCY)
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#else
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#ifdef CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
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# define BOARD_CLOCK_FREQUENCY (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * 1000000)
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#else
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# define BOARD_CLOCK_FREQUENCY 80000000
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#endif
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#endif
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#endif /* __BOARDS_XTENSA_ESP32_ESP32_CORE_INCLUDE_BOARD_H */
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