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nuttx/arch/xtensa/include
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zhuyanlin 9ea7676731 arch:xtensa: rename XCHAL_INT_NLEVELS to XCHAL_NUM_INTLEVELS 
The name used in Tensilica support file core-isa.h for all vendors is
`XCHAL_NUM_INTLEVELS`.
Use a new name may be confused by newer porting xtensa arch.

Change-Id: Ie108d3fdfcc02c81f0eacfca852a1cfc9eea17de
2021-08-28 21:51:45 +02:00
..
esp32 arch:xtensa: rename XCHAL_INT_NLEVELS to XCHAL_NUM_INTLEVELS 2021-08-28 21:51:45 +02:00
esp32s2 arch:xtensa: rename XCHAL_INT_NLEVELS to XCHAL_NUM_INTLEVELS 2021-08-28 21:51:45 +02:00
lx6 arch: xtensa: Author Gregory Nutt: update licenses to Apache 2021-04-02 03:14:31 -05:00
lx7 Add initial ESP32S2 Xtensa support 2021-06-01 07:49:54 +02:00
xtensa xtensa:coproc: fix XTENSA_CP_ALLSET error in some case 2021-08-10 19:44:55 -07:00
.gitignore Remove exra whitespace from files (#189) 2020-01-31 09:24:49 -06:00
arch.h arch: Rename xxx_getsp to up_getsp 2021-06-09 10:20:02 -07:00
elf.h xtensa: Implement a few relocations 2020-03-16 07:54:49 -06:00
inttypes.h xtensa inttypes.h: Remove PRI/SCN macros for fast and least types 2020-11-05 18:49:22 -08:00
irq.h arch/xtensa: Move the Xtensa specific part of interrupts to 2021-08-26 07:06:22 +09:00
limits.h arch: xtensa: Author Gregory Nutt: update licenses to Apache 2021-04-02 03:14:31 -05:00
loadstore.h esp32: emulate byte access for module text 2020-03-16 07:54:49 -06:00
simcall.h xtensa: Implement simcall 2020-03-12 09:03:31 -05:00
spinlock.h arch&boards/xtensa: Fix some typos, references to STM/ARM code and 2020-08-27 05:48:55 -07:00
stdarg.h arch:xtensa: add arch stdarg.h include file for xtensa 2021-08-09 17:58:25 -03:00
syscall.h arch: xtensa: Author Gregory Nutt: update licenses to Apache 2021-04-02 03:14:31 -05:00
tls.h arch: Rename xxx_getsp to up_getsp 2021-06-09 10:20:02 -07:00
types.h arch: xtensa: Author Gregory Nutt: update licenses to Apache 2021-04-02 03:14:31 -05:00